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RP2350 is a 32-bit dual-core microcontroller (containing selectable ARM Cortex-M33 and/or Hazard3 RISC-V cores) by Raspberry Pi Ltd. [1] In August 2024, it was released as part of the Raspberry Pi Pico 2 board. [2]
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RP2350 is a 32-bit dual-core microcontroller (containing selectable ARM Cortex-M33 and/or Hazard3 RISC-V cores) by Raspberry Pi Ltd. [1] In August 2024, it was released as part of the Raspberry Pi Pico 2 board. [2]
Announced on 8 August 2024, the RP2350 is the second microcontroller designed by Raspberry Pi Ltd, after the RP2040. [2] The microcontroller is low cost, with the Raspberry Pi Pico 2 being introduced at US$5 and the RP2350 itself costing as little as US$0.80 in bulk. The microcontroller is software-compatible with the RP2040 and can be programmed in assembly, C, C++, Free Pascal, Rust, MicroPython, CircuitPython, and other languages.
The RP2350 comes in four versions, which are identified by the number of cores (2), a numeral loosely correlated to the core type [3] (3), log₂ of the number of 16 KB RAM blocks (5), log₂ of the number of 128 KB flash storage blocks (0 or 4), and a letter denoting package type (A or B): [4]
Note: inside the "54" IC packages, a NOR flash die is stacked on top of the microcontroller die, then connected to its QSPI bus and first chip select.
At announcement time, seventeen other manufacturers had products expected to be available within a month.[ citation needed ]
The RP2350 chip is a 5.3-by-5.3-millimetre (0.21 in × 0.21 in) silicon die in either a 7 mm × 7 mm (0.28 in × 0.28 in) QFN-60EP or a 10 mm × 10 mm (0.39 in × 0.39 in) QFN-80EP surface-mount device (SMD) package. [2]
The following is a simplified comparison of the RP2040 and RP2350 microcontroller families.
| Feature | RP2040 | RP2350 |
|---|---|---|
| Package | QFN-56EP | QFN-60EP or QFN-80EP |
| CPU Cores | 2 × ARM Cortex-M0+ | 2 × ARM Cortex-M33 (w/FPU) |
| 2 × Hazard3 RISC-V | ||
| CPU Clock | 200 MHz [5] | 150 MHz |
| SRAM | 264 KB, 6 banks | 520 KB, 10 banks |
| Flash | None | None (RP2350), 2 MB (RP2354) |
| OTP | None | 8 KB |
| DMA | 12 chan, 2 IRQ | 16 chan, 4 IRQ |
| PIO | 2 (8 state machines) | 3 (12 state machines) |
| PWM | 16 | 24 |
| ADC | 4-chan 12-bit ADC | 4-chan 12-bit (QFN-60EP), 8-chan 12-bit (QFN-80EP) |
| DAC | None | None |
| HSTX | None | One |
| Engines | ? | RNG, SHA-256 |
The RP2350 chip was released with errata RP2350-E9, documenting a "Latching behaviour on Bank 0 GPIO pull-down resistors", which was later updated to "Increased leakage current on Bank 0 GPIO when pad input is enabled" due to multiple reports from users, [6] such as developers of the Bus Pirate.
The defect causes pins configured as inputs to source about 120 μA when the input voltage is between logical low and logical high, pulling them to about 2.2V. [7]
Luke Wren, one of the engineers working on RP2350 has stated that the supplier responsible for the pad circuitry has provided a faulty design. "We didn't modify the pad, we asked the vendor to modify their own pad. There was one particular structure on the RP2040 FT pad that limited its tolerance, but on inspection the modified layout we got back was a completely different circuit." [8]
The issue was resolved in the A3 and A4 stepping level versions of the chips, announced in July 2025. [9]
The RP2350 chip integrates security features like secure boot and OTP. To assess the level of security of their implementation, Raspberry Pi Foundation launch a hacking contest during DEF CON 32 offering US$10,000 to anyone able to read the OTP memory of the RP2350 chip. [10] After 30 days, nobody submitted a vulnerability so the foundation double the prize and extended the deadline. In January 2025, the foundation announced four winners of the challenges. [11] Various attacks were performed like secure boot bypass using laser fault injection or read out of the OTP value using a Focused Ion Bean.
