Ian A. Young

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Ian A. Young
Ian Young Intel Senior Fellow Picture.jpg
Born
Melbourne, Australia
NationalityAmerican
Alma mater University of California, Berkeley, University of Melbourne, Australia
Known for Phase-locked loop
AwardsFellow, IEEE 1999; Fellow Intel 1996, Senior Fellow Intel 2004
Scientific career
Institutions Intel, University of California, Berkeley, Mostek
Thesis MOS switched-capacitor analogue sampled-data recursive filters  (1978)
Doctoral advisor David A. Hodges, Paul R. Gray, Donald Pederson (postdoc)

Ian A. Young is an Intel engineer. [1] Young is a co-author of 50 research papers, [2] and has 71 patents [3] in switched capacitor circuits, DRAM, SRAM, BiCMOS, x86 clocking, Photonics and spintronics.

Contents

Biography

Born in Melbourne, Australia, Young received his bachelor's and master's degrees in electrical engineering from the University of Melbourne, Australia. He received his PhD in electrical engineering from the University of California, Berkeley in 1978, where he did research on MOSFET switched-capacitor filters. [4]

Technical career

Early career, analog MOS integrated circuits and switched capacitor filters

Young obtained his PhD from University of California, Berkeley in 1978, working with David A. Hodges, developing the switched MOS capacitor circuits. [4] [5]

Intel BiCMOS for Logic and SRAM

Young started at Intel in 1983 with the development of circuits for 1 Mb DRAM in 1 μm CMOS in 1985, [6] and first 64 K SRAM in 1 μm CMOS. This was also the first military qualified SRAM under the VHIC program. [7] At 600 nanometre node, Intel adopted BiCMOS for logic requiring the development of a BiCMOS SRAM for cache and a new family of standard logic circuits. The BiCMOS logic family employed the npn devices in the pull-up path of the BiCMOS gate, to form a low power CMOS logic family with high capacitive drive capability. Intel's BiCMOS technology was enabled by an innovative triple diffused npn transistor. This led to a highly manufacturable low cost process due to minimum number of additional process steps. In contrast, other companies employed BiCMOS to implement emitter-coupled logic for microprocessors, which consumed much more power. The BiCMOS circuits were developed for the Pentium processor family and its follow-on generations, Pentium Pro, Pentium II processor family.

Pentium era and clock scaling

Young developed a Phase Locked Loop (PLL) based clocking circuit in a microprocessor while working on the 50 MHz Intel 80486 processor design. He subsequently developed the core PLL clocking circuit building blocks used in each generation of Intel microprocessors through the 0.13 μm 3.2 GHz Pentium 4. The successful introduction of GHz clocking contributed to improvements in computing power.

The 486DX2 architecture showing on board PLL and clock 80486DX2 arch.svg
The 486DX2 architecture showing on board PLL and clock
Intel CPU clock scaling Clock CPU Scaling.jpg
Intel CPU clock scaling

The integration of an on-chip PLL enabled the clock rates to exceed the off chip interconnect I/O rate in DX2. This led to the integration of an on-chip cache, paving the path for the first microprocessor with 1 million transistors.

The clock rate scaling ushered by Intel and AMD ended as the thermal power dissipation of processors reached 100 W/cm^2. By the end of the race for clock speed, the clock rates had increased by a factor of more than 50. Intel subsequently shifted to multi-core era with modified Intel Core architecture and concurrent improvements in cache sizes to take advantage of the continued success of Moore's law.

Beyond CMOS computing

He is the founding editor-in-chief of IEEE Journal of Exploratory Solid State Computational Devices.

Awards and honours

Selected works

Selected patents

Related Research Articles

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References

  1. ↑ "Intel Leadership Website". Newsroom.intel.com. Retrieved 27 February 2013.
  2. ↑ "List of peer reviewed papers". Google Scholar. 15 February 2005. Retrieved 27 February 2013.
  3. ↑ "List of Patents" . Retrieved 27 February 2013.
  4. 1 2 Young, I. A. MOS switched-capacitor analog sampled-data recursive filters (Thesis). University of California, Berkeley. p. 27. Bibcode:1978PhDT........27Y.
  5. ↑ Young, I.A.; Hodges, D.A. (December 1979). "MOS switched-capacitor analog sampled-data direct-form recursive filters". IEEE Journal of Solid-State Circuits. 14 (6): 1020–1033. Bibcode:1979IJSSC..14.1020Y. doi:10.1109/JSSC.1979.1051311. S2CID   39918017.
  6. ↑ Webb, C; Creek, R; Holt, W; King, G; Young, I (1986). "A 65 ns CMOS 1Mb DRAM". 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. pp. 262–263. doi:10.1109/ISSCC.1986.1156984. S2CID   60833533.
  7. ↑ "first military certified very high speed IC, pp 76". Archived from the original on 8 April 2013. Retrieved 27 February 2013.
  8. 1 2 3 4 5 "IEEE Society News". IEEE Solid-State Circuits Magazine. Vol. 1, no. 1 (Winter ed.). 2009. doi:10.1109/MSSC.2008.930947.
  9. 1 2 "Intel Appoints New Fellows". Embedded. Retrieved 27 February 2013.
  10. ↑ "Fellows: Y". IEEE. Retrieved 27 February 2013.
  11. ↑ "About: 2009 Conference Awards". ISSCC. Archived from the original on 11 December 2010. Retrieved 27 February 2013.
  12. ↑ Young, I.A.; Greason, J.K.; Wong, K.L. (1992). "A PLL clock generator with 5 to 110 MHz of lock range for microprocessors". IEEE Journal of Solid-State Circuits. 27 (11): 1599–1607. Bibcode:1992IJSSC..27.1599Y. doi:10.1109/4.165341.
  13. ↑ Young, I.A.; Mar, M.F.; Bhushan, B. (1997). "A 0.35 μm CMOS 3-880 MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors". 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers. pp. 330–331. doi:10.1109/ISSCC.1997.585406. ISBN   978-0-7803-3721-3. S2CID   41446239.
  14. ↑ Young, I.A.; Hodges, D.A. (27 September 2011). "MOS switched-capacitor analog sampled-data direct-form recursive filters". IEEE Journal of Solid-State Circuits. 14 (6): 1020–1033. doi:10.1109/JSSC.1979.1051311. S2CID   39918017.
  15. ↑ "A History of the Continuously Innovative Analog Integrated Circuit". Ieee.org. Retrieved 27 February 2013.
  16. ↑ Young, Ian A.; Mohammed, Edris; Liao, Jason T. S.; Kern, Alexandra M.; Palermo, Samuel; Block, Bruce A.; Reshotko, Miriam R.; Chang, Peter L.D. (27 September 2011). "Optical I/O Technology for Tera-Scale Computing". IEEE Journal of Solid-State Circuits. 45: 235–248. doi:10.1109/JSSC.2009.2034444.
  17. ↑ Muthali, H.S.; Thomas, T.P.; Young, I.A. (27 September 2011). "A CMOS 10-gb/S SONET transceiver". IEEE Journal of Solid-State Circuits. 39 (7): 1026–1033. CiteSeerX   10.1.1.136.2741 . doi:10.1109/JSSC.2004.829935. S2CID   13558998.
  18. ↑ Manipatruni, S.; Lipson, M.; Young, I. A. (27 September 2011). "Device Scaling Considerations for Nanophotonic CMOS Global Interconnects". IEEE Journal of Selected Topics in Quantum Electronics. 19 (2): 8200109. arXiv: 1207.6819 . doi:10.1109/JSTQE.2013.2239262. S2CID   6589733.
  19. ↑ Nikonov; Young (1 February 2013). "Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking". arXiv: 1302.0244 [cond-mat.mes-hall].
  20. ↑ Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic (Report). 1996 IEEE International Symposium on Circuits and Systems (ISCAS). June 2011. pp. 124–125. doi:10.1109/ISCAS.1996.598467. S2CID   62083760.
  21. ↑ ["http://journals.aps.org/prapplied/abstract/10.1103/PhysRevApplied.5.014002]
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