The UNIVAC LARC, short for the Livermore Advanced Research Computer, is a mainframe computer designed to a requirement published by Edward Teller in order to run hydrodynamic simulations for nuclear weapon design. It was one of the earliest supercomputers. [1] It used solid-state electronics.
The LARC architecture supported multiprocessing with two CPUs (called Computers) and an input/output (I/O) Processor (called the Processor). Two LARC machines were built, the first delivered to Livermore in June 1960, and the second to the Navy's David Taylor Model Basin. Both examples had only one CPU, so no multiprocessor LARCs were ever built. [2] Livermore decommissioned their LARC in December 1968 [3] and the Navy's LARC was turned off in April 1969. [4]
The LARC CPUs were able to perform addition in about 4 microseconds, corresponding to about 250 kIPS speed. This made it the fastest computer in the world until 1962 when the IBM 7030 Stretch took the title. The 7030 started as IBM's entry to the LARC contest, but Teller chose the simpler Univac over the riskier IBM design.
The LARC was a decimal mainframe computer with 60 bits per word. It used bi-quinary coded decimal arithmetic with five bits per digit (see below), allowing for 11-digit signed numbers. Instructions were 60 bits long, one per word. The basic configuration had 26 general-purpose registers, which could be expanded to 99. The general-purpose registers had an access time of one microsecond.
LARC weighed about 115,000 pounds (58 short tons; 52 t). [5]
The basic configuration had one Computer and LARC could be expanded to a multiprocessor with a second Computer.
The Processor is an independent CPU (with a different instruction set from the Computers) and provides control for 12 to 24 magnetic drum storage units, four to forty UNISERVO II tape drives, two electronic page recorders (a 35mm film camera facing a cathode-ray tube), one or two high-speed printers, and a high-speed punched card reader.
The LARC used core memory banks of 2500 words each, housed four banks per memory cabinet. The basic configuration had eight banks of core (two cabinets), 20,000 words. The memory could be expanded to a maximum of 39 banks of core (ten cabinets with one empty bank), 97,500 words. The core memory had one parity bit on each digit for error checking, resulting in 60 bits per memory word. The core memory had an access time of 8 microseconds and a cycle time of 4 microseconds. Each bank operated independently and could begin a new access in any 4-microsecond cycle when it was not already busy. By properly interleaving accesses to different banks the memory could sustain an effective access time of 4 microseconds on each access (e.g., instruction access in one bank data in another).
The data transfer bus connecting the two Computers and the Processor to the core memory was multiplexed to maximize throughput; every 4-microsecond bus cycle was divided into eight 500-nanosecond time slots:
The core memory system enforces a system of interlocks and priorities to avoid simultaneous access of the same memory bank by multiple sections of the system (the Computers, Processor, and I/O DMA Synchronizers) without conflicts or deadlocks. A memory bank is unavailable for one 4-microsecond cycle after being addressed by any section of the system. If another section attempts to address the same memory bank during this time, it is locked out and must wait, then try again in the next 4-microsecond cycle. To prevent deadlocks and timeouts in the I/O system the following priorities are enforced:
If a higher-priority section is locked out in one 4-microsecond cycle, when it tries again in the next 4-microsecond cycle, all lower-priority sections are prevented from beginning a new cycle on that memory bank until the higher-priority section has completed its access.
The LARC's Computers wrote lists of Summary Orders in memory for the Processor to read and interpret by the Processor Control Program (written and supplied by UNIVAC with each system), to request needed I/O. [6]
The LARC was built using surface-barrier transistors, which were already obsolete by the time the first system was delivered. The LARC was a very fast computer for its time. Its addition time was 4 microseconds, multiplication time was 8 microseconds, and the division time was 28 microseconds. It was the fastest computer in 1960–61, until the IBM 7030 took the title.
In the basic five-bit biquinary code of the UNIVAC-LARC, 15 combinations are allowed, any one of which may be stored in any digit position in storage. [7]
BIT POSITIONS
| CHARACTER |
---|---|
1 1 1 0 0 | \ (ignore) |
0 0 1 0 0 | ^ (space) |
0 0 0 1 0 | - (minus) |
1 0 0 0 0 | 0 |
0 0 0 0 1 | 1 |
1 0 0 1 1 | 2 |
0 0 1 1 1 | 3 |
1 0 1 1 0 | 4 |
0 1 0 0 0 | 5 |
1 1 0 0 1 | 6 |
0 1 0 1 1 | 7 |
1 1 1 1 1 | 8 |
0 1 1 1 0 | 9 |
1 1 0 1 0 | . (period) |
1 0 1 0 1 | + (plus) |
Direct memory access (DMA) is a feature of computer systems that allows certain hardware subsystems to access main system memory independently of the central processing unit (CPU).
The CDC 6600 was the flagship of the 6000 series of mainframe computer systems manufactured by Control Data Corporation. Generally considered to be the first successful supercomputer, it outperformed the industry's prior recordholder, the IBM 7030 Stretch, by a factor of three. With performance of up to three megaFLOPS, the CDC 6600 was the world's fastest computer from 1964 to 1969, when it relinquished that status to its successor, the CDC 7600.
The IBM 7030, also known as Stretch, was IBM's first transistorized supercomputer. It was the fastest computer in the world from 1961 until the first CDC 6600 became operational in 1964.
The IBM 701 Electronic Data Processing Machine, known as the Defense Calculator while in development, was IBM’s first commercial scientific computer and its first series production mainframe computer, which was announced to the public on May 21, 1952. It was designed and developed by Jerrier Haddad and Nathaniel Rochester and was based on the IAS machine at Princeton.
The UNIVAC 1100/2200 series is a series of compatible 36-bit computer systems, beginning with the UNIVAC 1107 in 1962, initially made by Sperry Rand. The series continues to be supported today by Unisys Corporation as the ClearPath Dorado Series. The solid-state 1107 model number was in the same sequence as the earlier vacuum-tube computers, but the early computers were not compatible with their solid-state successors.
The IBM 700/7000 series is a series of large-scale (mainframe) computer systems that were made by IBM through the 1950s and early 1960s. The series includes several different, incompatible processor architectures. The 700s use vacuum-tube logic and were made obsolete by the introduction of the transistorized 7000s. The 7000s, in turn, were eventually replaced with System/360, which was announced in 1964. However the 360/65, the first 360 powerful enough to replace 7000s, did not become available until November 1965. Early problems with OS/360 and the high cost of converting software kept many 7000s in service for years afterward.
The HP 2100 is a series of 16-bit minicomputers that were produced by Hewlett-Packard (HP) from the mid-1960s to early 1990s. Tens of thousands of machines in the series were sold over its twenty-five year lifetime, making HP the fourth largest minicomputer vendor during the 1970s.
The Intel 8087, announced in 1980, was the first floating-point coprocessor for the 8086 line of microprocessors. The purpose of the chip was to speed up floating-point arithmetic operations, such as addition, subtraction, multiplication, division, and square root. It also computes transcendental functions such as exponential, logarithmic or trigonometric calculations. The performance enhancements were from approximately 20% to over 500%, depending on the specific application. The 8087 could perform about 50,000 FLOPS using around 2.4 watts.
KDF9 was an early British 48-bit computer designed and built by English Electric. The first machine came into service in 1964 and the last of 29 machines was decommissioned in 1980 at the National Physical Laboratory. The KDF9 was designed for, and used almost entirely in, the mathematical and scientific processing fields – in 1967, nine were in use in UK universities and technical colleges. The KDF8, developed in parallel, was aimed at commercial processing workloads.
In computing, a word is the natural unit of data used by a particular processor design. A word is a fixed-sized datum handled as a unit by the instruction set or the hardware of the processor. The number of bits or digits in a word is an important characteristic of any specific processor design or computer architecture.
The UNIVAC III, designed as an improved transistorized replacement for the vacuum tube UNIVAC I and UNIVAC II computers. The project was started by the Philadelphia division of Remington Rand UNIVAC in 1958 with the initial announcement of the system been made in the Spring of 1960, however as this division was heavily focused on the UNIVAC LARC project the shipment of the system was delayed until June 1962, with Westinghouse agreeing to furnish system programing and marketing on June 1, 1962. It was designed to be compatible for all data formats. However the word size and instruction set were completely different; this presented significant difficulty as all programs had to be rewritten, so many customers switched to different vendors instead of upgrading existing UNIVACs.
In computing, channel I/O is a high-performance input/output (I/O) architecture that is implemented in various forms on a number of computer architectures, especially on mainframe computers. In the past, channels were generally implemented with custom devices, variously named channel, I/O processor, I/O controller, I/O synchronizer, or DMA controller.
IBM 7070 is a decimal-architecture intermediate data-processing system that was introduced by IBM in 1958. It was part of the IBM 700/7000 series, and was based on discrete transistors rather than the vacuum tubes of the 1950s. It was the company's first transistorized stored-program computer.
In computing, traditionally cycle stealing is a method of accessing computer memory (RAM) or bus without interfering with the CPU. It is similar to direct memory access (DMA) for allowing I/O controllers to read or write RAM without CPU intervention. Clever exploitation of specific CPU or bus timings can permit the CPU to run at full speed without any delay if external devices access memory not actively participating in the CPU's current activity and complete the operations before any possible CPU conflict.
The CDC 6000 series is a discontinued family of mainframe computers manufactured by Control Data Corporation in the 1960s. It consisted of the CDC 6200, CDC 6300, CDC 6400, CDC 6500, CDC 6600 and CDC 6700 computers, which were all extremely rapid and efficient for their time. Each is a large, solid-state, general-purpose, digital computer that performs scientific and business data processing as well as multiprogramming, multiprocessing, Remote Job Entry, time-sharing, and data management tasks under the control of the operating system called SCOPE. By 1970 there also was a time-sharing oriented operating system named KRONOS. They were part of the first generation of supercomputers. The 6600 was the flagship of Control Data's 6000 series.
The CDC 160 series was a series of minicomputers built by Control Data Corporation. The CDC 160 and CDC 160-A were 12-bit minicomputers built from 1960 to 1965; the CDC 160G was a 13-bit minicomputer, with an extended version of the CDC 160-A instruction set, and a compatibility mode in which it did not use the 13th bit. The 160 was designed by Seymour Cray - reportedly over a long three-day weekend. It fit into the desk where its operator sat.
The history of general-purpose CPUs is a continuation of the earlier history of computing hardware.
The RCA Spectra 70 is a line of electronic data processing (EDP) equipment that was manufactured by the Radio Corporation of America’s computer division beginning in April 1965. The Spectra 70 line included several CPU models, various configurations of core memory, mass-storage devices, terminal equipment, and a variety of specialized interface equipment.
A vacuum-tube computer, now termed a first-generation computer, is a computer that uses vacuum tubes for logic circuitry. While the history of mechanical aids to computation goes back centuries, if not millennia, the history of vacuum tube computers is confined to the middle of the 20th century. Lee De Forest invented the triode in 1906. The first example of using vacuum tubes for computation, the Atanasoff–Berry computer, was demonstrated in 1939. Vacuum-tube computers were initially one-of-a-kind designs, but commercial models were introduced in the 1950s and sold in volumes ranging from single digits to thousands of units. By the early 1960s vacuum tube computers were obsolete, superseded by second-generation transistorized computers.
Philco was one of the pioneers of transistorized computers, also known as second generation computers. After the company developed the surface barrier transistor, which was much faster than previous point-contact types, it was awarded contracts for military and government computers. Commercialized derivatives of some of these designs became successful business and scientific computers. The TRANSAC Model S-1000 was released as a scientific computer. The TRANSAC S-2000 mainframe computer system was first produced in 1958, and a family of compatible machines, with increasing performance, was released over the next several years.
After their installation, the two systems remained in continuous use until December 1968, when the Lawrence Radiation Laboratory retired its LARC system which had been operated on a 7-day-per-week, 24-hour-per-day schedule.