 | |
| Formation | March 2006 |
|---|---|
| Type | Industry trade group |
| Purpose | Flash memory standardization |
| Website | www |
The Open NAND Flash Interface Working Group (ONFI or ONFi [1] with a lower case "i") is a consortium of technology companies working to develop open standards for NAND flash memory and devices that communicate with them. The formation of ONFI was announced at the Intel Developer Forum in March 2006. [2]
The group's goals did not include the development of a new consumer flash memory card format. [3] Rather, ONFI seeks to standardize the low-level interface to raw NAND flash chips, which are the most widely used form of non-volatile memory integrated circuits (chips); in 2006, nearly one trillion MiB of flash memory was incorporated into consumer electronics, and production was expected to double by 2007. [4] As of 2006 [update] , NAND flash memory chips from most vendors used similar packaging, had similar pinouts, and accepted similar sets of low-level commands. As a result, when more capable and inexpensive models of NAND flash become available, product designers can incorporate them without major design changes. However, "similar" operation is not optimal: [5] subtle differences in timing and command set mean that products must be thoroughly debugged and tested when a new model of flash chip is used in them. [4] When a flash controller is expected to operate with various NAND flash chips, it must store a table of them in its firmware so that it knows how to deal with differences in their interfaces. [4] [5] This increases the complexity and time-to-market of flash-based devices, and means they are likely to be incompatible with future models of NAND flash, unless and until their firmware is updated.
Thus, one of the main motivations for standardization of NAND flash was to make it easier to switch between NAND chips from different producers, thereby permitting faster development of NAND-based products and lower prices via increased competition among manufacturers. By 2006, NAND flash became increasingly a commodity product, [6] like SDRAM or hard disk drives. It is incorporated into many personal computer and consumer electronics products such as USB flash drives, MP3 players, and solid-state drives. Product designers wanted newer NAND flash chips, for example, to be as easily interchangeable as hard disks from different manufacturers. [6] [7]
The effort to standardize NAND flash may be compared to earlier standardization of electronic components. For example, the 7400 series of TTL digital integrated circuits were originally produced by Texas Instruments, but had become a de facto standard family by the late 1970s. These ICs are manufactured as commodity parts by a number of different vendors. This has allowed designers to freely mix 7400 components from different vendors—and even to mix components based on different logic families, once the 74HCT sub-family become available (consisting of CMOS components with TTL-compatible logic levels).
The ONFI consortium included manufacturers of NAND flash memory such as Hynix, Intel, Micron Technology, Phison, Western Digital, Sony and Spansion. [2] Samsung, the world's largest manufacturer of NAND flash, was absent in 2006. [8] Vendors of NAND flash-based consumer electronics and computing products are also members.
ONFI produced specifications for standard interface to NAND flash chips.
Version 1.0 of this specification was released on December 28, 2006, and made available at no cost from the ONFI web site. Samsung was still not a participant. [9] It specified:
A verification product was announced in June 2009. [10]
Version 2.3 was published in August 2010. It included a protocol called EZ-NAND that hid ECC details. [11]
Version 3.0 was published in March 2011. It required fewer chip-enable pins enabling more efficient printed circuit board routing. [12] A standard developed jointly with the JEDEC was published in October 2012. [13] [14]
Version 3.1, published in october of 2012, includes errata to the original ONFI 3.0 specification, adds LUN SET/GET Features commands, and implements additional data setup and hold values for NV-DDR2 interface.
Version 3.2, published on July 23, 2013, raised the data rate to 533 MB/s. [15]
Version 4.0, published on April 17, 2014, introduced the NV-DDR3 interface increases the maximum switching speed from 533 MB/s to 800 MB/s, providing a performance boost of up to 50% for high performance applications enabled by solid-state NAND storage components. [16]
Version 4.1, published on December 12, 2017, extends NV-DDR3 I/O speeds to 1066 MT/s and 1200MT/s. [17] For better signaling performance, ONFI 4.1 adds Duty Cycle Correction (DCC), Read and Write Training for speeds greater than 800MT/s, support for lower pin cap devices with 37.5 Ohms default output resistance, and devices which require data burst exit and restart for long data input and output pauses. For lower power, 2.5V Vcc support is added. ONFI 4.1 also includes errata to the ONFI 4.0 specification.
Version 4.2, published on February 12, 2020, extends NV-DDR3 I/O speeds to 1333MT/s, 1466MT/s and 1600MT/s. The BGA-252b four channel package is introduced which has a smaller footprint than the existing BGA-272b four channel package. To enable higher IOPS multi-plane operations, addressing restrictions related to multi-plane operations are relaxed. [18]
Version 5.0, Published in May 2021, ONFI5.0 extends NV-DDR3 I/O speeds up to 2400MT/s. A new NV-LPDDR4 lower power interface is introduced with speeds up to 2400MT/s. With the NV-LPDDR4 interface, an optional Data Bus Inversion (DBI) feature is defined. New smaller footprint BGA-178b, BGA-154b and BGA-146b packages are added. ONFI5.0 also includes other errata related to the ONFI4.2 specification. [19]
ONFI created the Block Abstracted NAND addendum specification to simplify host controller design by relieving the host of the complexities of ECC, bad block management, and other low-level NAND management tasks. The ONFI Block Abstracted NAND revision 1.1 specification adds the high speed source synchronous interface, which provides up to a 5X improvement in bandwidth compared with the traditional asynchronous NAND interface. [20]
The NAND Connector Specification was ratified in April 2008. It specifies a standardized connection for NAND modules (similar to DRAM DIMMs) for use in applications like caching and solid-state drives (SSDs) in PC platforms.
Double Data Rate Synchronous Dynamic Random-Access Memory is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called DDR1 SDRAM, has been superseded by DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM and DDR5 SDRAM. None of its successors are forward or backward compatible with DDR1 SDRAM, meaning DDR2, DDR3, DDR4 and DDR5 memory modules will not work on DDR1-equipped motherboards, and vice versa.
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