SPARC T4

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Oracle SPARC T4 Oracle SPARC T4 chip 028.jpg
Oracle SPARC T4
SPARC T4
General information
Launched2011
Performance
Max. CPU clock rate 2.85 GHz to 3.0 GHz
Cache
L1 cache 8×(16+16) kB
L2 cache8×128 kB
L3 cache4 MB
Architecture and classification
Min. feature size 40 nm
Instruction set SPARC V9
Physical specifications
Cores
  • 8
Products, models, variants
Core name(s)
  • S3
History
Predecessor SPARC T3
Successor SPARC T5

The SPARC T4 is a SPARC multicore microprocessor introduced in 2011 by Oracle Corporation. The processor is designed to offer high multithreaded performance (8 threads per core, with 8 cores per chip), as well as high single threaded performance from the same chip. [1] The chip is the 4th generation [2] processor in the T-Series family. Sun Microsystems brought the first T-Series processor (UltraSPARC T1) to market in 2005.

Contents

The chip is the first Sun/Oracle SPARC chip to use dynamic threading [3] and out-of-order execution. [4] It incorporates one floating point unit and one dedicated cryptographic unit per core. [2] The cores use the 64-bit SPARC Version 9 architecture running at frequencies between 2.85 GHz and 3.0 GHz, and are built in a 40  nm process with a die size of 403 mm2 (0.625 sq in). [1]

History and design

An eight core, eight thread per core chip built in a 40 nm process and running at 2.5 GHz was described in Sun Microsystems' processor roadmap of 2009. It was codenamed "Yosemite Falls" and given an expected release date of late 2011. The processor was expected to introduce a new microarchitecture, codenamed "VT Core". The online technology website The Register speculated that this chip would be named "T4", being the successor to the SPARC T3. [5] The Yosemite Falls CPU product remained on Oracle Corporation's processor roadmap after the company took over Sun in early 2010. [6] In December 2010 the T4 processor was confirmed by Oracle's VP of hardware development to be designed for improved per-thread performance, with eight cores, and with an expected release within one year. [7] [8]

The processor design was presented at the 2011 Hot Chips conference. [9] The cores (renamed "S3" from "VT") included a dual-issue 16 stage integer pipeline, and 11-cycle floating point pipeline, both giving improvements over the previous ("S2") core used in the SPARC T3 processor. Each core has associated 16 KB data and 16 KB instruction L1 caches, and a unified 128 KB L2 Cache. All eight cores share 4 MB L3 cache, and the total transistor count is approximately 855 million. [9] The design was the first Sun/Oracle SPARC processor with out-of-order execution [10] and was the first processor in the SPARC T-Series family to include the ability to issue more than one instruction per cycle to a core's execution units. [11]

The T4 processor was officially introduced as part of Oracle's SPARC T4 servers in September 2011. [12] Initial product releases of a single processor T4-1 rack server ran at 2.85 GHz. [3] The dual processor T4-2 ran at the same 2.85 GHz frequency, and the quad processor T4-4 server ran at 3.0 GHz. [13]

The SPARC S3 core also include a thread priority mechanism (called "dynamic threading") whereby each thread is allocated resources based on need, giving increased performance. [9] Most S3 core resources are shared among all active threads, up to 8 of them. Shared resources include branch prediction structures, various buffer entries, and out-of-order execution resources. Static resource allocation reserves the resources to the threads based on a policy whether the thread can use them or not. Dynamic threading allocates these resources to the threads that are ready and will use them, thus improving performance. [4]

Cryptographic performance was also increased over the T3 chip by design improvements including a new set of cryptographic instructions. [8] UltraSPARC T2 and T3's per-core cryptographic coprocessors were replaced with in-core accelerators and instruction-based cryptography. The implementation is designed to achieve wire speed encryption and decryption on the SPARC T4's 10-Gbit/s Ethernet ports. [4]

The architectural changes are claimed to deliver a 5x improvement in single thread integer performance [9] and twice the per-thread throughput performance compared to the previous generation T3. [4] The published SPECjvm2008 result for a 16-core T4-2 is 454 ops/m [14] and 321 ops/m [15] for the 32-core T3-2 which is a ratio of 2.8x in performance per core.

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SPARC

SPARC is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from a number of vendors through the 1980s and 90s.

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UltraSPARC T1

Sun Microsystems' UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename "Niagara", is a multithreading, multicore CPU. Designed to lower the energy consumption of server computers, the CPU typically uses 72 W of power at 1.4 GHz.

Multi-core processor Microprocessor with more than one processing unit

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Rock (processor)

Rock was a multithreading, multicore, SPARC microprocessor under development at Sun Microsystems. Canceled in 2010, it was a separate project from the SPARC T-Series (CoolThreads/Niagara) family of processors.

UltraSPARC T2

Sun Microsystems' UltraSPARC T2 microprocessor is a multithreading, multi-core CPU. It is a member of the SPARC family, and the successor to the UltraSPARC T1. The chip is sometimes referred to by its codename, Niagara 2. Sun started selling servers with the T2 processor in October 2007.

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SPARC T3

The SPARC T3 microprocessor is a multithreading, multi-core CPU produced by Oracle Corporation. Officially launched on 20 September 2010, it is a member of the SPARC family, and the successor to the UltraSPARC T2.

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The SPARC T-series family of RISC processors and server computers, based on the SPARC V9 architecture, was originally developed by Sun Microsystems, and later by Oracle Corporation after its acquisition of Sun. Its distinguishing feature from earlier SPARC iterations is the introduction of chip multithreading (CMT) technology, a multithreading, multicore design intended to drive greater processor utilization at lower power consumption.

SPARC T5

SPARC T5 is the fifth generation multicore microprocessor of Oracle's SPARC T-Series family. It was first presented at Hot Chips 24 in August 2012, and was officially introduced with the Oracle SPARC T5 servers in March 2013. The processor is designed to offer high multithreaded performance, as well as high single threaded performance from the same chip.

References

  1. 1 2 SPARC T4 Processor Data Sheet (PDF), Oracle Corporation
  2. 1 2 Jean S. Bozman; Matthew Eastwood (April 2012), SPARC Servers: An Effective Choice for Efficiency in the Datacenter, p. 9 (PDF), IDC
  3. 1 2 Timothy Prickett Morgan (27 September 2011), "Oracle rises for Unix server push", www.theregister.co.uk, The Register, pp. 1–2
  4. 1 2 3 4 Manish Shah; Robert Golla; Gregory Grohoski; Paul Jordan; Jama Barreh; Jeff Brooks; Mark Greenberg; Gideon Levinsky; Mark Luttrell; Christopher Olson; Zeid Samoail; Matt Smittle; Tom Ziaja (March–April 2012), IEEE Micro, vol. 32, no. 2, Sparc T4: A Dynamically Threaded Server-on-a-Chip, pp. 8-19, IEEE Computer Society
  5. ↑ Timothy Prickett Morgan (11 September 2009), "Sun's Sparc server roadmap revealed", www.theregister.co.uk, The Register, pp. 1–2
  6. ↑ Timothy Prickett Morgan (28 January 2010), "Oracle to invest in Sparc iron, clusters", www.register.co.uk, The Register, pp. 1–2
  7. ↑ Timothy Prickett Morgan (23 December 2010), "Oracle revisits Sparc T processor roadmap", www.theregister.co.uk, The Register
  8. 1 2 Diana Reichardt (ed.), "Rick Hetherington : Oracle Innovation Showcase (Conversations with Oracle Innovators)", www.oracle.com, Oracle Corporation
  9. 1 2 3 4 Robert Golla; Paul Jordan (August 19, 2011), T4: A Highly Threaded Server-on-a-Chip with Native Support for Heterogeneous Computing (PDF), Hot Chips
  10. ↑ Nick Farrell (28 September 2011), "Oracle's Ellison spins SPARC T4", news.techeye.net, TechEye, archived from the original on 31 July 2014, retrieved 28 September 2011
  11. ↑ Oracle's SPARC T4-1, SPARC T4-2, SPARC T4-4, and SPARC T4-1B Server Architecture (PDF), Oracle Corporation
  12. ↑ Matthew Finnegan, "Oracle lords it over HP and IBM with SPARC T4", news.techeye.net, TechEye, archived from the original on 2011-09-29
  13. ↑ SPARC T4-4 Server Data Sheet (PDF), Oracle Corporation
  14. ↑ SPECjvm2008 Peak, Oracle SPARC T4-2, Oracle Corporation, November 2011
  15. ↑ SPECjvm2008 Peak, Oracle SPARC T3-2, Oracle Corporation, October 2010
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