Surface activated bonding

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Surface activated bonding (SAB) is a non-high-temperature wafer bonding technology with atomically clean and activated surfaces. Surface activation prior to bonding by using fast atom bombardment is typically employed to clean the surfaces. High-strength bonding of semiconductor, metal, and dielectric can be obtained even at room temperature. [1] [2]

Contents

Overview

In the standard SAB method, wafer surfaces are activated by argon fast atom bombardment in ultra-high vacuum (UHV) of 10−4–10−7 Pa. The bombardment removes adsorbed contaminants and native oxides on the surfaces. The activated surfaces are atomically clean and reactive for formation of direct bonds between wafers when they are brought into contact even at room temperature.

Researches on SAB

The SAB method has been studied for bonding of various materials, as shown in Table I.

Table I. Studies of standard SAB for various materials
SiGeGaAsSiCCuAl2O3SiO2
Si [3] [4] [5] [6] [7] [8]
Ge [9]
GaAs [5] [10]
SiC [6] [10] [11]
Cu [12] [13]
Al2O3 [7] [8] [7]
SiO2Failure [7]

The standard SAB, however, failed to bond some materials such as SiO2 and polymer films. The modified SAB was developed to solve this problem, by using a sputtering deposited Si intermediate layer to improve the bond strength.

Table II. Modified SAB with Si intermediate layer
Bonding intermediate layerReferences
SiO2-SiO2Sputtered Fe-Si on SiO2 [14]
Polymer filmsSputtered Fe-Si on both sides [15] [16] [17]
Si-SiCSputtered Si on SiC [18]
Si-SiO2Sputtered Si on SiO2 [19]

The combined SAB has been developed for SiO2-SiO2 and Cu/SiO2 hybrid bonding, without use of any intermediate layer.

Table III. Combined SAB using Si-containing Ar beam
Bond interfaceReferences
SiO2-SiO2Direct bond interface [20]
Cu-Cu, SiO2-SiO2, SiO2-SiNxdirect bond interface [21]

Technical specifications

Materials
Advantages
  • Low process temperature: room temperature–200 °C
  • No concerns of thermal stress and damages
  • High bonding quality
  • Semiconductor and metal bonding interfaces without oxides
  • Completely dry process without wet chemical cleaning
  • Process compatibility to semiconductor technology
Drawbacks
  • High vacuum level (10−4–10−7 Pa)

Related Research Articles

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