Keshab K. Parhi

Last updated
Keshab K. Parhi (1999). VLSI Digital Signal Processing Systems: Design and Implementation. Wiley-Interscience. ISBN   978-0-471-24186-7.

Parhi has also authored over 725 papers and is inventor or co-inventor of 36 issued US patents. [31]

Professional service

Parhi has served the Institute of Electrical and Electronics Engineers (IEEE) in various capacities. He has served as Associate Editor for numerous transactions published by the IEEE Circuits and Systems Society and the IEEE Signal Processing Society. His leadership roles include: [1]

Distinctions and awards

  • 2017 – IEEE Circuits and Systems Society Mac Van Valkenburg Award for pioneering contributions to VLSI digital signal processing architectures, design methodologies, and their applications to wired and wireless communications, and service to IEEE Circuits and Systems Society [38]
  • 2012 – IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award for contributions to VLSI architectures and design methodologies for digital signal processing and communications circuits and systems. [41]
  • 2003 – IEEE Kiyo Tomiyasu Award for pioneering contributions to high-speed and low-power digital signal processing architectures for broadband communications systems [43]
  • 1996 – Fellow, IEEE for contributions to the fields of VLSI digital signal processing architectures, design methodologies and tools [45]

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References

  1. 1 2 3 4 5 6 "Keshab K. Parhi Homepage". www.ece.umn.edu. Retrieved 26 December 2024.
  2. ↑ "NSF-CGP Fellowship: VLSI Digital Signal Processing and Multimedia Systems". www.nsf.gov. Retrieved 26 December 2024.
  3. ↑ "SBIR Awards". sbir.gov. Retrieved 18 January 2025.
  4. ↑ Parhi, K.K. (December 1989). "Algorithm Transformation Techniques for Concurrent Processors". Proceedings of the IEEE. 77 (12): 1879–1895. doi:10.1109/5.48830.
  5. ↑ Parhi, K.K.; Messerschmitt, D.G. (February 1991). "Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding". IEEE Transactions on Computers. 40 (2): 178–195. doi:10.1109/12.73588.
  6. ↑ Parhi, K.K.; Wang, C.-Y.; Brown, A.P. (January 1992). "Synthesis of Control Circuits in Folded Pipelined DSP Architectures". IEEE Journal of Solid-State Circuits. 27 (1): 29–43. Bibcode:1992IJSSC..27...29P. doi:10.1109/4.109555.
  7. ↑ Parhi, K.K.; Messerschmitt, D.G. (July 1989). "Pipeline Interleaving and Parallelism in Recursive Digital Filters, Part I: Pipelining using Scattered Look-Ahead and Decomposition". IEEE Transactions on Acoustics, Speech, and Signal Processing. 37 (7): 1099–1117. doi:10.1109/29.32286.
  8. ↑ Parhi, K.K.; Messerschmitt, D.G. (July 1989). "Pipeline Interleaving and Parallelism in recursive Digital Filters, Part II: Pipelined Incremental Block Filtering". IEEE Transactions on Acoustics, Speech, and Signal Processing. 37 (7): 1118–1134. doi:10.1109/29.32287.
  9. ↑ Parhi, K.K.; Messerschmitt, D.G. (October 1987). "Concurrent Cellular VLSI Adaptive Filter Architectures". IEEE Transactions on Circuits and Systems. 34 (10): 1141–1151. doi:10.1109/TCS.1987.1086048.
  10. ↑ Shanbhag, N.R.; Parhi, K.K. (December 1993). "Relaxed Look-Ahead Pipelined LMS Adaptive Filters and Their Application to ADPCM Coder". IEEE Transactions on Circuits and Systems, Part II: Analog and Digital Signal Processing. 40 (12): 753–766. doi:10.1109/82.260240.
  11. ↑ Parhi, K.K. (July 1991). "Pipelining in Algorithms with Quantizer Loops". IEEE Transactions on Circuits and Systems. 38 (7): 745–754. doi:10.1109/31.135746.
  12. ↑ Parhi, K.K. (April 2005). "Design of Multi-Gigabit Multiplexer Loop Based Decision Feedback Equalizers". IEEE Transactions on VLSI Systems. 13 (4): 489–493. doi:10.1109/TVLSI.2004.842935.
  13. ↑ Gu, Y.; Parhi, K.K. (September 2007). "High-Speed Architecture Design of Tomlinson-Harashima Precoders". IEEE Transactions on Circuits and Systems, Part I: Regular Papers. 54 (9): 1929–1937. doi:10.1109/TCSI.2007.904688.
  14. ↑ Gu, Y.; Parhi, K.K. (May 2008). "Design of Parallel Tomlinson-Harashima Precoders". IEEE Transactions on Circuits and Systems, Part II: Express Briefs. 55 (5): 447–451. doi:10.1109/TCSII.2007.914435.
  15. ↑ Gu, Y.; Parhi, K.K. (February 2007). "Pipelined Parallel Decision Feedback Decoders for High-Speed Ethernet over Copper". IEEE Transactions on Signal Processing. 55 (2): 707–715. Bibcode:2007ITSP...55..707G. doi:10.1109/TSP.2006.885776.
  16. ↑ Cheng, C.; Parhi, K.K. (October 2007). "High-Throughput VLSI Architecture for FFT Computation". IEEE Transactions on Circuits and Systems II: Express Briefs. 54 (10): 863–867. doi:10.1109/TCSII.2007.901635.
  17. ↑ Ayinala, M.; Brown, M.J.; Parhi, K.K. (June 2012). "Pipelined Parallel FFT Architectures via Folding Transformation". IEEE Transactions on VLSI Systems. 20 (6): 1068–1081. doi:10.1109/TVLSI.2011.2147338.
  18. ↑ Parhi, K.K. (April 2024). A Low-Latency FFT-IFFT Cascade Architecture. Proc. of 2024 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). pp. 181–185. arXiv: 2309.09035 . doi:10.1109/ICASSP48485.2024.10447370.
  19. ↑ Wang, Z.; Chi, Z.; Parhi, K.K. (December 2002). "Area-Efficient High Speed Decoding Schemes for Turbo/MAP Decoders". IEEE Transactions on VLSI Systems. 10 (12): 902–912. doi:10.1109/TVLSI.2002.808451.
  20. ↑ Zhang, T.; Parhi, K.K. (April 2004). "Joint (3,k)-regular LDPC Code and Decoder/Encoder Design". IEEE Transactions on Signal Processing. 52 (4): 1065–1079. Bibcode:2004ITSP...52.1065Z. doi:10.1109/TSP.2004.823508.
  21. ↑ Chen, Y.; Parhi, K.K. (June 2004). "Overlapped Message Passing for Quasi-Cyclic Low-Density Parity Check Codes". IEEE Transactions on Circuits and Systems I: Regular Papers. 51 (6): 1106–1113. doi:10.1109/TCSI.2004.826194.
  22. ↑ Yuan, B.; Parhi, K.K. (April 2014). "Low-Latency Successive-Cancellation Polar Decoder Architectures using 2-bit Decoding". IEEE Transactions on Circuits and Systems I: Regular Papers. 61 (4): 1241–1254. doi:10.1109/TCSI.2013.2283779.
  23. ↑ Yuan, B.; Parhi, K.K. (December 15, 2014). "Early Stopping Criteria for Energy-Efficient Low-Latency Belief-Propagation Polar Code Decoders". IEEE Transactions on Circuits and Systems I: Regular Papers. 62 (24): 6496–6506. Bibcode:2014ITSP...62.6496Y. doi:10.1109/TSP.2014.2366712.
  24. ↑ Zhang, X.; Parhi, K.K. (September 2004). "High-Speed VLSI Architectures for the AES Algorithm". IEEE Transactions on VLSI Systems. 12 (9): 957–967. doi:10.1109/TVLSI.2004.832943.
  25. ↑ Tan, W.; Wang, A.; Zhang, X.; Lao, Y.; Parhi, K.K. (September 2023). "High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography". IEEE Transactions on Computers. 72 (9): 2454–2466. arXiv: 2110.12127 . doi:10.1109/TC.2023.3251847.
  26. ↑ Tan, W.; Chiu, S.-W.; Wang, A.; Lao, Y.; Parhi, K.K. (January 2024). "PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption". IEEE Transactions on Information Forensics and Security. 19: 1646–1659. arXiv: 2303.02237 . doi:10.1109/TIFS.2023.3338553.
  27. ↑ Lao, Y.; Parhi, K.K. (May 2015). "Obfuscating DSP Circuits via High-Level Transformations". IEEE Transactions on VLSI Systems. 23 (5): 819–830. doi:10.1109/TVLSI.2014.2323976.
  28. ↑ Koteshwara, S.; Kim, C.H.; Parhi, K.K. (January 2018). "Key-Based Dynamic Functional Obfuscation of Integrated Circuits using Sequentially-Triggered Mode-Based Design". IEEE Transactions on Information Forensics and Security. 13 (1): 79–93. doi:10.1109/TIFS.2017.2738600.
  29. ↑ Wang, C.-Y.; Parhi, K.K. (March 1995). "High-Level DSP Synthesis using Concurrent Transformations, Scheduling, and Allocation". IEEE Transactions on Computer Aided Design. 14 (3): 274–295. doi:10.1109/43.365120.
  30. ↑ Satyanarayana, J.; Parhi, K.K. (June 1996). HEAT: Hierarchical Energy Analysis Tool. ACM/IEEE Design Automation Conference. pp. 9–14. doi:10.1109/DAC.1996.545536.
  31. ↑ "Keshab K. Parhi - Google Scholar". scholar.google.com. Retrieved 30 December 2024.
  32. ↑ "Charles E. Bowers Faculty Teaching Award, UMN CSE". cse.umn.edu. Retrieved 26 December 2024.
  33. ↑ "Dr. Keshab Parhi Elected to the 2022 Class of the AIMBE College of Fellows" (PDF). aimbe.org. Retrieved 26 December 2024.
  34. ↑ "IEEE Circuits and Systems Society John Choma Education Award Recipients". ieee-cas.org. Retrieved 26 December 2024.
  35. ↑ "2020 ACM Fellows Recognized for Work that Underpins Today's Computing Innovations". www.acm.org. Retrieved 26 December 2024.
  36. ↑ "U of M Professor Keshab Parhi to be inducted into the National Academy of Inventors". twin-cities.umn.edu. 8 December 2020. Retrieved 26 December 2024.
  37. ↑ "2017 AAAS Fellows Recognized for Advancing Science". www.aaas.org. Retrieved 26 December 2024.
  38. ↑ "IEEE Circuits and Systems Society Mac Van Valkenburg Award Recipients". ieee-cas.org. Retrieved 26 December 2024.
  39. ↑ "Distinguished Alumni Awards List". www.iitkgpfoundation.org. Retrieved 26 December 2024.
  40. ↑ "Keshab Parhi - Scholars Walk". scholarswalk.umn.edu. Retrieved 30 December 2024.
  41. ↑ "IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award Recipients". ieee-cas.org. Retrieved 26 December 2024.
  42. ↑ "Division Awards Archive, Electrical and Computer Engineering Division". monolith.asee.orgorg. Retrieved 26 December 2024.
  43. ↑ "IEEE Kiyo Tomiyasu Award". ethw.org. 2 December 2024. Retrieved 30 December 2024.
  44. ↑ "IEEE W.R.G. Baker Award". ethw.org. 2 December 2024. Retrieved 30 December 2024.
  45. ↑ "IEEE Fellows Directory". services27.ieee.org. Retrieved 26 December 2024.
  46. ↑ "NYI: Dedicated VLSI Digital Signal and Image Processors". www.nsf.gov. Retrieved 26 December 2024.
  47. ↑ "IEEE Browder J. Thompson Memorial Prize Paper Award". ethw.org. 19 February 2019. Retrieved 26 December 2024.
  48. ↑ "IEEE Signal Processing Society Young Author Best Paper Award" (PDF). signalprocessingsociety.org. Retrieved 26 December 2024.
  49. ↑ "Eli Jury Award". www2.eecs.berkeley.edu. Retrieved 26 December 2024.
  50. ↑ "Demetri Angelakos Memorial Achievement Award". www2.eecs.berkeley.edu. Retrieved 26 December 2024.
Keshab K. Parhi
Born1959 (1959)
Bhadrak District, Odisha, India
CitizenshipUnited States
Awards
Academic background
Alma mater
Thesis Algorithm and Architecture Design for High-Speed Signal Processing  (1988)
Doctoral advisor David G. Messerschmitt
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