Resolution enhancement technologies

Last updated July 22, 2024

Resolution enhancement technologies are methods used to modify the photomasks in the lithographic processes used to make integrated circuits (ICs or "chips") to compensate for limitations in the optical resolution of the projection systems. These processes allow the creation of features well beyond the limit that would normally apply due to the Rayleigh criterion. Modern technologies allow the creation of features on the order of 5 nanometers (nm), far below the normal resolution possible using deep ultraviolet (DUV) light.

Background

Integrated circuits are created in a multi-step process known as photolithography. This process starts with the design of the IC circuitry as a series of layers than will be patterned onto the surface of a sheet of silicon or other semiconductor material known as a wafer.

Each layer of the ultimate design is patterned onto a photomask, which in modern systems is made of fine lines of chromium deposited on highly purified quartz glass. Chromium is used because it is highly opaque to UV light, and quartz because it has limited thermal expansion under the intense heat of the light sources as well as being highly transparent to ultraviolet light. The mask is positioned over the wafer and then exposed to an intense UV light source. With a proper optical imaging system between the mask and the wafer (or no imaging system if the mask is sufficiently closely positioned to the wafer such as in early lithography machines), the mask pattern is imaged on a thin layer of photoresist on the surface of the wafer and a light (UV or EUV)-exposed part of the photoresist experiences chemical reactions causing the photographic pattern to be physically created on the wafer.

When light shines on a pattern like that on a mask, diffraction effects occur. This causes the sharply focused light from the UV lamp to spread out on the far side of the mask and becoming increasingly unfocussed over distance. In early systems in the 1970s, avoiding these effects required the mask to be placed in direct contact with the wafer in order to reduce the distance from the mask to the surface. When the mask was lifted it would often pull off the resist coating and ruin that wafer. Producing a diffraction-free image was ultimately solved through the projection aligner systems, which dominated chip making through the 1970s and early 1980s.

The relentless drive of Moore's law ultimately reached the limit of what the projection aligners could handle. Efforts were made to extend their lifetimes by moving to ever-higher UV wavelengths, first to DUV and then to EUV, but the small amounts of light given off at these wavelengths made the machines impractical, requiring enormous lamps and long exposure times. This was solved through the introduction of the steppers, which used a mask at much larger sizes and used lenses to reduce the image. These systems continued to improve in a fashion similar to the aligners, but by the late 1990s were also facing the same issues.

At the time, there was considerable debate about how to continue the move to smaller features. Systems using excimer lasers in the soft-X-ray region were one solution, but these were incredibly expensive and difficult to work with. It was at this time that resolution enhancement began to be used.

Basic concept

The basic concept underlying the various resolution enhancement systems is the creative use of diffraction in certain locations to offset the diffraction in others. For instance, when light diffracts around a line on the mask it will produce a series of bright and dark lines, or "bands". that will spread out the desired sharp pattern. To offset this, a second pattern is deposited whose diffraction pattern overlaps with the desired features, and whose bands are positioned to overlap the original pattern's to produce the opposite effect - dark on light or vice versa. Multiple features of this sort are added, and the combined pattern produces the original feature. Typically, on the mask these additional features look like additional lines lying parallel to the desired feature.

Adding these enhancement features has been an area of continual improvement since the early 2000s. In addition to using additional patterning, modern systems add phase-shifting materials, multiple-patterning and other techniques. Together, they have allowed feature size to continue to shrink to orders of magnitude below the diffraction limit of the optics.

Using resolution enhancement

Traditionally, after an IC design has been converted into a physical layout, the timing verified, and the polygons certified to be DRC-clean, the IC was ready for fabrication. The data files representing the various layers were shipped to a mask shop, which used mask-writing equipment to convert each data layer into a corresponding mask, and the masks were shipped to the fab where they were used to repeatedly manufacture the designs in silicon. In the past, the creation of the IC layout was the end of the involvement of electronic design automation.

However, as Moore's law has driven features to ever-smaller dimensions, new physical effects that could be effectively ignored in the past are now affecting the features that are formed on the silicon wafer. So even though the final layout may represent what is desired in silicon, the layout can still undergo dramatic alteration through several EDA tools before the masks are fabricated and shipped. These alterations are required not to make any change in the device as designed, but to simply allow the manufacturing equipment, often purchased and optimized for making ICs one or two generations behind, to deliver the new devices. These alterations can be classed as being of two types.

The first type is distortion corrections, namely pre-compensating for distortions inherent in the manufacturing process, be it from a processing step, such as: photolithography, etching, planarization, and deposition. These distortions are measured and a suitable model fitted, compensation is carried out usually using a rule or model based algorithm. When applied to printing distortions during photolithography, this distortion compensation is known as Optical Proximity Correction (OPC).

The second type of Reticle Enhancement involves actually improving the manufacturability or resolution of the process. Examples of this include:

RET Technique	Manufacturability Improvement
Scattering Bars	Sub resolution assist features that improves the depth of focus of isolated features.
Phase-shift Mask	Etching quartz from certain areas of the mask (alt-PSM) or replacing Chrome with phase shifting Molybdenum Silicide layer (attenuated embedded PSM) to improve CD control and increase resolution
Double or Multiple Patterning	Involves decomposing the design across multiple masks to allow the printing of tighter pitches.

For each of these manufacturability improvement techniques there are certain layouts that either cannot be improved or cause issues in printing. These are classed as non-compliant layouts. These are avoided either at the design stage - using, for instance, Radically Restrictive Design Rules and/or creating addition DRC checks if appropriate. Both the lithographic compensations and manufacturability improvements are usually grouped under the heading resolution enhancement techniques (RET). Such techniques have been used since the 180nm node and have become more aggressively used as minimum feature size as dropped significantly below that of the imaging wavelength, currently limited to 13.5 nm.^[1]

This is closely related to, and a part of, the more general category of design for manufacturability (IC) or DFM.

After RET, the next step in an EDA flow is usually mask data preparation.

Related Research Articles

Photolithography is a process used in the manufacturing of integrated circuits. It involves using light to transfer a pattern onto a substrate, typically a silicon wafer.

A photomask is an opaque plate with transparent areas that allow light to shine through in a defined pattern. Photomasks are commonly used in photolithography for the production of integrated circuits to produce a pattern on a thin wafer of material. In semiconductor manufacturing, a mask is sometimes called a reticle.

Electron-beam lithography is the practice of scanning a focused beam of electrons to draw custom shapes on a surface covered with an electron-sensitive film called a resist (exposing). The electron beam changes the solubility of the resist, enabling selective removal of either the exposed or non-exposed regions of the resist by immersing it in a solvent (developing). The purpose, as with photolithography, is to create very small structures in the resist that can subsequently be transferred to the substrate material, often by etching.

The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect those transistors together. It is the primary process by which silicon integrated circuit chips are built, and it is the most commonly used method of producing junctions during the manufacture of semiconductor devices. The process utilizes the surface passivation and thermal oxidation methods.

Masklesslithography (MPL) is a photomask-less photolithography-like technology used to project or focal-spot write the image pattern onto a chemical resist-coated substrate by means of UV radiation or electron beam.

Nanolithography (NL) is a growing field of techniques within nanotechnology dealing with the engineering of nanometer-scale structures on various materials.

Extreme ultraviolet lithography is a new technology used in the semiconductor industry for manufacturing integrated circuits (ICs). It is a type of photolithography that uses extreme ultraviolet (EUV) light to create intricate patterns on silicon wafers.

Next-generation lithography or NGL is a term used in integrated circuit manufacturing to describe the lithography technologies in development which are intended to replace current techniques. Driven by Moore's law in the semiconductor industries, the shrinking of the chip size and critical dimension continues. The term applies to any lithography method which uses a shorter-wavelength light or beam type than the current state of the art, such as X-ray lithography, electron beam lithography, focused ion beam lithography, and nanoimprint lithography. The term may also be used to describe techniques which achieve finer resolution features from an existing light wavelength.

In semiconductor fabrication, a resist is a thin layer used to transfer a circuit pattern to the semiconductor substrate which it is deposited upon. A resist can be patterned via lithography to form a (sub)micrometer-scale, temporary mask that protects selected areas of the underlying substrate during subsequent processing steps. The material used to prepare said thin layer is typically a viscous solution. Resists are generally proprietary mixtures of a polymer or its precursor and other small molecules that have been specially formulated for a given lithography technology. Resists used during photolithography are called photoresists.

A stepper or wafer stepper is a device used in the manufacture of integrated circuits (ICs). It is an essential part of the process of photolithography, which creates millions of microscopic circuit elements on the surface of silicon wafers out of which chips are made. It is similar in operation to a slide projector or a photographic enlarger. The ICs that are made form the heart of computer processors, memory chips, and many other electronic devices.

Phase-shift masks are photomasks that take advantage of the interference generated by phase differences to improve image resolution in photolithography. There exist alternating and attenuated phase shift masks. A phase-shift mask relies on the fact that light passing through a transparent media will undergo a phase change as a function of its optical thickness.

Optical proximity correction (OPC) is a photolithography enhancement technique commonly used to compensate for image errors due to diffraction or process effects. The need for OPC is seen mainly in the making of semiconductor devices and is due to the limitations of light to maintain the edge placement integrity of the original design, after processing, into the etched image on the silicon wafer. These projected images appear with irregularities such as line widths that are narrower or wider than designed, these are amenable to compensation by changing the pattern on the photomask used for imaging. Other distortions such as rounded corners are driven by the resolution of the optical imaging tool and are harder to compensate for. Such distortions, if not corrected for, may significantly alter the electrical properties of what was being fabricated. Optical proximity correction corrects these errors by moving edges or adding extra polygons to the pattern written on the photomask. This may be driven by pre-computed look-up tables based on width and spacing between features or by using compact models to dynamically simulate the final pattern and thereby drive the movement of edges, typically broken into sections, to find the best solution,. The objective is to reproduce the original layout drawn by the designer on the semiconductor wafer as well as possible.

Contact lithography, also known as contact printing, is a form of photolithography whereby the image to be printed is obtained by illumination of a photomask in direct contact with a substrate coated with an imaging photoresist layer.

<span class="mw-page-title-main">LIGA</span> Fabrication technology used to create high-aspect-ratio microstructures

LIGA is a fabrication technology used to create high-aspect-ratio microstructures. The term is a German acronym for Lithographie, Galvanoformung, Abformung – lithography, electroplating, and molding.

Computational lithography is the set of mathematical and algorithmic approaches designed to improve the resolution attainable through photolithography. Computational lithography came to the forefront of photolithography technologies in 2008 when the semiconductor industry faced challenges associated with the transition to a 22 nanometer CMOS microfabrication process and has become instrumental in further shrinking the design nodes and topology of semiconductor transistor manufacturing.

In photolithography, off-axis illumination is an optical system setup in which the incoming light strikes a photomask at an oblique angle rather than perpendicularly to it, that is to say, the incident light is not parallel to the axis of the optical system.

Photolithography is a process in removing select portions of thin films used in microfabrication. Microfabrication is the production of parts on the micro- and nano- scale, typically on the surface of silicon wafers, for the production of integrated circuits, microelectromechanical systems (MEMS), solar cells, and other devices. Photolithography makes this process possible through the combined use of hexamethyldisilazane (HMDS), photoresist, spin coating, photomask, an exposure system and other various chemicals. By carefully manipulating these factors it is possible to create nearly any geometry microstructure on the surface of a silicon wafer. The chemical interaction between all the different components and the surface of the silicon wafer makes photolithography an interesting chemistry problem. Current engineering has been able to create features on the surface of silicon wafers between 1 and 100 μm.

Three-dimensional (3D) microfabrication refers to manufacturing techniques that involve the layering of materials to produce a three-dimensional structure at a microscopic scale. These structures are usually on the scale of micrometers and are popular in microelectronics and microelectromechanical systems.

An aligner, or mask aligner, is a system that produces integrated circuits (IC) using the photolithography process. It holds the photomask over the silicon wafer while a bright light is shone through the mask and onto the photoresist. The "alignment" refers to the ability to place the mask over precisely the same location repeatedly as the chip goes through multiple rounds of lithography.

The Perkin-Elmer Micralign was a family of aligners introduced in 1973. Micralign was the first projection aligner, a concept that dramatically improved semiconductor fabrication. According to the Chip History Center, it "literally made the modern IC industry".

References

↑ "EUV: Extreme Ultraviolet Lithography - Semiconductor Engineering".

Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and Scheffer, ISBN 0-8493-3096-3 A survey of the field, from which this summary was derived, with permission.

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[1] "EUV: Extreme Ultraviolet Lithography - Semiconductor Engineering".

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