Clock domain crossing

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In digital electronic design a clock domain crossing (CDC), or simply clock crossing, is the traversal of a signal in a synchronous digital circuit from one clock domain into another. If a signal does not assert long enough and is not registered, it may appear asynchronous on the incoming clock boundary. [1]

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A synchronous system is composed of a single electronic oscillator that generates a clock signal, and its clock domain—the memory elements directly clocked by that signal from that oscillator, and the combinational logic attached to the outputs of those memory elements.

Because of speed-of-light delays, timing skew, etc., the size of a clock domain in such a synchronous system is inversely proportional to the frequency of the clock. [2] In early computers, typically all the digital logic ran in a single clock domain. Because of transmission line loss and distortion it is difficult to carry digital signals above 66 MHz on standard PCB traces (the clock signal is the highest frequency in a synchronous digital system), CPUs that run faster than that speed invariably are single-chip CPUs with a phase-locked loop (PLL) or other on-chip oscillator, keeping the fastest signals on-chip. At first, each CPU chip ran in its own single clock domain, and the rest of the digital logic of the computer ran in another slower clock domain. A few modern CPUs have such a high speed clock, that designers are forced to create several different clock domains on a single CPU chip.[ when? ][ which? ]

Different clock domains have clocks which have a different frequency, a different phase (due to either differing clock latency or a different clock source), or both. [3] Either way the relationship between the clock edges in the two domains cannot be relied upon.

Synchronizing a single bit signal to a clock domain with a higher frequency can be accomplished by registering the signal through a flip-flop that is clocked by the source domain, thus holding the signal long enough to be detected by the higher frequency clocked destination domain.

CDC metastability issues can occur between asynchronous clock domains; this is in contrast to reset domain crossing metastability, which can occur between synchronous & asynchronous clock domains. [4] To avoid issues with CDC metastability in the destination clock domain, a minimum of 2 stages of re-synchronization flip-flops are included in the destination domain. Synchronizing a single bit signal traversing into clock domain with a slower frequency is more cumbersome. This typically requires a register in each clock domain with a form of feedback from the destination domain to the source domain, indicating that the signal was detected. [5] Other potential clock domain crossing design errors include glitches and data loss. [6]

In some cases, clock gating can result in two clock domains where the "slower" domain changes from one second to the next.

See also

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In digital electronics, synchronous circuit is a digital circuit in which the changes in the state of memory elements are synchronized by a clock signal. In a sequential digital logic circuit, data is stored in memory devices called flip-flops or latches. The output of a flip-flop is constant until a pulse is applied to its "clock" input, upon which the input of the flip-flop is latched into its output. In a synchronous logic circuit, an electronic oscillator called the clock generates a string (sequence) of pulses, the "clock signal". This clock signal is applied to every storage element, so in an ideal synchronous circuit, every change in the logical levels of its storage components is simultaneous. Ideally, the input to each storage element has reached its final value before the next clock occurs, so the behaviour of the whole circuit can be predicted exactly. Practically, some delay is required for each logical operation, resulting in a maximum speed limitations at which each synchronous system can run.

In digital electronics, an asynchronous circuit, clockless, or self-timed circuit, is a sequential digital logic circuit which is not governed by a clock circuit or global clock signal. Instead it often uses signals that indicate completion of instructions and operations, specified by simple data transfer protocols. This type of circuit is contrasted with synchronous circuits, in which changes to the signal values in the circuit are triggered by repetitive pulses called a clock signal. Most digital devices today use synchronous circuits. However asynchronous circuits have the potential to be faster, and may also have advantages in lower power consumption, lower electromagnetic interference, and better modularity in large systems. Asynchronous circuits are an active area of research in digital logic design.

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Metastability (electronics)

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A frequency divider, also called a clock divider or scaler or prescaler, is a circuit that takes an input signal of a frequency, , and generates an output signal of a frequency:

Globally asynchronous locally synchronous (GALS) is an architecture for designing electronic circuits which addresses the problem of safe and reliable data transfer between independent clock domains. GALS is a model of computation that emerged in the 1980s. It allows to design computer systems consisting of several synchronous islands interacting with other islands using asynchronous communication, e.g. with FIFOs.

Flip-flop (electronics)

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information – a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are fundamental building blocks of digital electronics systems used in computers, communications, and many other types of systems.

In computing, a logic block or configurable logic block (CLB) is a fundamental building block of field-programmable gate array (FPGA) technology. Logic blocks can be configured by the engineer to provide reconfigurable logic gates.

References

  1. ↑ Parker, Roy H. (2004-06-02). "Caution: Clock Crossing – A prescription for uncontaminated data across clock domains". Chip Design Magazine – Tools, Technologies & Methodologies. No. 5. Extension Media, Inc. Article 32. Archived from the original on 2019-03-27.
  2. ↑ Seitz, Charles L. (December 1979) [1978-07-23]. "Chapter 7: System Timing" (PDF). In Mead, Carver; Conway, Lynn (eds.). Introduction to VLSI Design (1 ed.). Addison Wesley. ISBN   0-20104358-0. ISBN   978-0-20104358-7. Archived (PDF) from the original on 2020-06-19. Retrieved 2020-08-06. (46 pages) (NB. Cf. isochronous region.)
  3. ↑ Asic World: Interfacing Two Clock Domains
  4. ↑ BTV: Reset Domain Crossing Sign-Off Fundamentals
  5. ↑ Stein, Mike (2003-07-24). "Crossing the abyss: asynchronous signals in a synchronous world – as digital design becomes increasingly sophisticated, circuits with multiple clocks must reliably communicate with each other" (PDF). EDN . Paradigm Works, Andover, Massachusetts, USA. pp. 59–60, 62, 64, 66, 68–69. Archived (PDF) from the original on 2020-08-06. Retrieved 2020-08-06. (7 pages)
  6. ↑ SemiEngineering: Clock Domain Crossing (CDC)

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