PowerPC e200

Last updated May 03, 2019

The PowerPC e200 is a family of 32-bit Power ISA microprocessor cores developed by Freescale for primary use in automotive and industrial control systems. The cores are designed to form the CPU part in system-on-a-chip (SoC) designs with speed ranging up to 600 MHz, thus making them ideal for embedded applications.

In computer architecture, 32-bit integers, memory addresses, or other data units are those that are 32 bits wide. Also, 32-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size. 32-bit microcomputers are computers in which 32-bit microprocessors are the norm.

Power ISA Computer instruction set architecture

The Power ISA is an instruction set architecture (ISA) developed by the OpenPOWER Foundation, led by IBM. It was originally developed by the now defunct Power.org industry group. Power ISA is an evolution of the PowerPC ISA, created by the mergers of the core PowerPC ISA and the optional Book E for embedded applications. The merger of these two components in 2006 was led by Power.org founders IBM and Freescale Semiconductor. The ISA is divided into several categories and every component is defined as a part of a category; each category resides within a certain Book. Processors implement a set of these categories. Different classes of processors are required to implement certain categories, for example a server class processor includes the categories Base, Server, Floating-Point, 64-Bit, etc. All processors implement the Base category.

A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit (IC), or at most a few integrated circuits. The microprocessor is a multipurpose, clock driven, register based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory and provides results as output. Microprocessors contain both combinational logic and sequential digital logic. Microprocessors operate on numbers and symbols represented in the binary number system.

The e200 core is developed from the MPC5xx family processors, which in turn is derived from the MPC8xx core in the PowerQUICC SoC processors. e200 adheres to the Power ISA v.2.03 as well as the previous Book E specification. All e200 core based microprocessors are named in the MPC55xx and MPC56xx/JPC56x scheme, not to be confused with the MPC52xx processors which is based on the PowerPC e300 core.

The MPC5xx family of processors such as the MPC555 and MPC565 are 32-bit PowerPC embedded microprocessors that operate between 40 and 66 MHz and are frequently used in automotive applications including engine and transmission controllers. Delphi Corporation use either the MPC561 or MPC565 in the engine controllers they supply to General Motors, with nearly all 2009 model GM North America vehicles now using an MPC5xx in the engine controller. Bosch also used the MPC5xx throughout the EDC-16 series of Diesel Engine Controllers as did the Cummins B series diesel engine ECU.

PowerQUICC is the name for several PowerPC- and Power ISA-based microcontrollers from Freescale Semiconductor. They are built around one or more PowerPC cores and the Communications Processor Module which is a separate RISC core specialized in such tasks such as I/O, communications, ATM, security acceleration, networking and USB. Many components are System-on-a-chip designs tailor made for embedded applications.

The PowerPC e300 is a family of 32-bit PowerPC microprocessor cores developed by Freescale for primary use in system-on-a-chip (SoC) designs with speed ranging up to 800 MHz, thus making them ideal for embedded applications.

In April 2007 Freescale and IPextreme opened up the e200 cores for licensing to other manufacturers.^[1]

Continental AG and Freescale are developing SPACE, a tri-core e200 based processor designed for electronic brake systems in cars.^[2]

Continental AG, commonly known as Continental, is a German automotive manufacturing company specializing in, brake systems, interior electronics, automotive safety, powertrain and chassis components, tachographs, tires and other parts for the automotive and transportation industries. Continental is based in Hanover, Lower Saxony, Germany. Continental is the world's fourth-largest tire manufacturer.

STMicroelectronics and Freescale have jointly developed microcontrollers for automotive applications based on e200 in the MPC56xx/SPC56x family.

STMicroelectronics is a French-Italian multinational electronics and semiconductor manufacturer headquartered in Geneva, Switzerland. It is commonly called ST, and it is Europe's largest semiconductor chip maker based on revenue. While STMicroelectronics corporate headquarters and the headquarters for EMEA region are based in Geneva, the holding company, STMicroelectronics N.V. is registered in Amsterdam, Netherlands.

Cores

The e200 family consists of six cores, from simple low-end to complex high-end in nature.

e200z0

The simplest core, e200z0 features an in order, four stage pipeline. It has no MMU, no cache, and no FPU. It uses the variable bit length (VLE) part of the Power ISA, which uses 16-bit versions of the otherwise standard 32-bit PowerPC Book E ISA, thus reducing code footprint by up to 30%. It has a single 32-bit AMBA 2.0v6 bus interface. The load/store unit is pipelined, has a 1-cycle load latency and supports throughput of one load or store operation per cycle.

In computer engineering, out-of-order execution is a paradigm used in most high-performance central processing units to make use of instruction cycles that would otherwise be wasted. In this paradigm, a processor executes instructions in an order governed by the availability of input data and execution units, rather than by their original order in a program. In doing so, the processor can avoid being idle while waiting for the preceding instruction to complete and can, in the meantime, process the next instructions that are able to run immediately and independently.

A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware unit having all memory references passed through itself, primarily performing the translation of virtual memory addresses to physical addresses.

The ARM Advanced Microcontroller Bus Architecture (AMBA) is an open-standard, on-chip interconnect specification for the connection and management of functional blocks in system-on-a-chip (SoC) designs. It facilitates development of multi-processor designs with large numbers of controllers and peripherals with a bus architecture. Since its inception, the scope of AMBA has, despite its name, gone far beyond microcontroller devices. Today, AMBA is widely used on a range of ASIC and SoC parts including applications processors used in modern portable mobile devices like smartphones. AMBA is a registered trademark of ARM Ltd.

The e200z0 is used in the MPC5510 as an optional co-processor alongside an e200z1 core, making that chip a multicore processor. e200z0 is available as co-processors to other e200 based processors as well as very low end stand alone processors.

e200z1

The e200z1 has a four-stage, single-issue pipeline with a branch prediction unit and an 8 entry MMU, no cache and no FPU. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a dual 32-bit AMBA 2.0v6 bus interface. The load/store unit is pipelined, has a 1-cycle load latency and supports throughput of one load or store operation per cycle.

e200z3

The e200z3 has a four-stage, single-issue pipeline with a branch prediction unit, a 16 entry MMU and a SIMD capable FPU. It has no cache. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a dual 64-bit AMBA 2.0v6 bus interface. The load/store unit is pipelined, has a 1-cycle load latency and supports throughput of one load or store operation per cycle.

e200z4

The e200z4 has a five-stage, dual-issue pipeline with a branch prediction unit, a 16 entry MMU, signal processing extension (SPE), a SIMD capable single precision FPU and a 4 Kilobyte 2/4-way set associative instruction L1 cache (Pseudo round-robin replacement algorithm). It has no data cache. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a dual 64-bit bus AMBA 2.0v6 interface. The load/store unit is pipelined, has a 2-cycle load latency and supports throughput of one load or store operation per cycle.

Depending on the derivative may support SPE or LSP.

e200z6

The e200z6 has a seven-stage, single-issue pipeline with a branch prediction unit, a 32 entry MMU, signal processing extensions (SPE), a SIMD capable single-precision FPU and an 8-way set associative 32 KiB unified data/instruction L1 cache. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a single 64-bit bus AMBA 2.0v6 interface. The load/store unit is pipelined, has a 3-cycle load latency and supports throughput of one load or store operation per cycle.

e200z7

The e200z7 has a ten-stage, dual-issue pipeline with a branch prediction unit, a 32 entry MMU, a SIMD capable single-precision FPU and 16-KB, 4 way set-associative Harvard instruction and data L1 caches. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a 32-bit bus AMBA 2.0v6 interface for the address bus, and a 64-bit data bus (plus attributes and control on each bus). The load/store unit is pipelined, has a 3-cycle load latency and supports throughput of one load or store operation per cycle.

Depending on the derivative may support SPE, SPE v1.1 or SPE v2.

Related Research Articles

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The Amber processor core is an ARM architecture-compatible 32-bit reduced instruction set computing (RISC) processor. It is open source, hosted on the OpenCores website, and is part of a movement to develop a library of open source hardware projects.

References

↑ "Freescale opens licensing of Power Architecture e200 core family through IPextreme" (Press release). April 2, 2007. Archived from the original on October 24, 2007.
↑ "Freescale and Continental collaborate on multi-core 32-bit microcontroller for electronic braking systems" (Press release). October 16, 2007. Archived from the original on July 12, 2012.

Freescale's MPC55xx page
ST's SPC5 page
IPextremes e200 licensing page
Freescale’s e200 Core Family, Overview and Licensing Model, White paper
Multi-Core Design: Key Challenges and Opportunities – Power.org
Halfhill, Tom R. (2 April 2007). "Freescale Licenses Power Cores". Microprocessor Report .

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[1] "Freescale opens licensing of Power Architecture e200 core family through IPextreme" (Press release). April 2, 2007. Archived from the original on October 24, 2007.

[2] "Freescale and Continental collaborate on multi-core 32-bit microcontroller for electronic braking systems" (Press release). October 16, 2007. Archived from the original on July 12, 2012.