| POWER, PowerPC, and Power ISA architectures |
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| NXP (formerly Freescale and Motorola) |
| IBM |
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| IBM/Nintendo |
| Other |
| Related links |
| Cancelled in gray, historic in italic |
The PowerPC e6500 is a multithreaded 64-bit Power ISA-based microprocessor core from Freescale Semiconductor (now part of NXP). The e6500 core powers the entire range of T2 family and T4 family QorIQ AMP Series system on a chip (SoC) processors. Hard samples, manufactured on a 28nm process, were available in early 2012. Full production of the QorIQ T2 and T4 family SoCs were commenced in the later months of 2012.
The T2 family and T4 family of QorIQ AMP Series SoCs have a revised cache hierarchy and CPU core arrangement, compared to T1-family SoCs which contain four PowerPC e5500 cores combined into a CPU cluster sharing a large L2 cache.
The e6500 core is the first multithreaded core designed by Freescale and reintroduces an enhanced version of AltiVec to their products. It supports up to eight multi-core CPU clusters for very large multiprocessing implementations. Multithreading allows for two virtual cores per hard core and is organized as 2x2-way superscalar. [1] One virtual core in an e6500 often performs better than an entire e5500 core since Freescale essentially duplicated a lot of logic instead of just virtualizing it, in addition to other enhancements to the core.
Each e6500 core contains five integer units (four simple and one complex), two load-store units, one 128-bit AltiVec unit, 32KB of L1 instruction cache and 32KB of L1 data cache. CPU core clock speeds range up to 2.5 GHz. The core is designed to be highly configurable via the CoreNet fabric and meet the specific needs of embedded applications, with features such as multi-core operation and interfaces for auxiliary application processing units (APU).
The e6501 core is a revision of the e6500 core introduced in 2013 with enhanced virtualization interrupt support. [2]