Types of physical unclonable function

Last updated

Physical unclonable function (PUF), sometimes also called physically unclonable function, is a physical entity that is embodied in a physical structure and is easy to evaluate but hard to predict.

Contents

All PUFs are subject to environmental variations such as temperature, supply voltage and electromagnetic interference, which can affect their performance. Therefore, rather than just being random, the real power of a PUF is its ability to be different between devices, but simultaneously to be the same under different environmental conditions.

PUF categorization

Measurement process

One way to categorise the numerous PUF concepts is by how the source of variation within each PUF is measured. [1] For instance some PUFs examine how the source of uniqueness interacts with, or influences, an electronic signal to derive the signature measurement while others examine the effects on the reflection of incident light, or another optical process. This also typically correlates with the intended application for each PUF concept. As an example, PUFs that probe uniqueness through electronic characterization are most suitable for authenticating electronic circuits or components due to the ease of integration. On the other hand, PUFs that authenticate physical objects tend to probe the PUF using a second process, such as optical or radio frequency methods, that are then converted into electronic signal forming a hybrid measurement system. This allows for easier communication at a distance between the separate physical authenticating tag or object and the evaluating device.

Randomness source

One major way that PUFs are categorized is based on examining from where the randomness or variation of the device is derived. [2] This source of uniqueness is either applied in an explicit manner, through the deliberate addition of extra manufacturing steps, or occurring in an implicit manner, as part of the typical manufacture processes. For example, in the case of electronic PUFs manufactured in CMOS, adding additional CMOS components is possible without introducing extra fabrication steps, and would count as an implicit source of randomness, as would deriving randomness from components that were already part of the design to start with. Adding, for example, a randomized dielectric coating for the sole purpose of PUF fingerprinting would add additional manufacturing steps and would make the PUF concept or implementation fall into the explicit category. Implicit randomness sources show benefit in that they do not have additional costs associated with introducing more manufacturing steps, and that randomness derived from the inherent variation of the device’s typical manufacture process cannot be as directly manipulated. Explicit randomness sources can show benefit in that the source of randomness can be deliberately chosen, for instance to maximize variation (and therefore entropy yield) or increase cloning difficulty (for example harnessing randomness from smaller feature sizes).

Intrinsic evaluation

In a similar manner to the classification of a PUF by its randomness source, PUF concepts can be divided by whether or not they can evaluate in an intrinsic manner. [3] A PUF is described as intrinsic if its randomness is of implicit origin and can evaluate itself internally. This means that the mechanism for characterizing the PUF is intrinsic to, or embedded within, the evaluating device itself. This property can currently only be held by PUFs of entirely electronic design, as the evaluation processing can only be done through the involvement of electronic circuitry, and therefore can only be inseparable to an electronic randomness probing mechanism. Intrinsic evaluation is beneficial as it can allow this evaluation processing and post-processing (such as error correction or hashing) to occur without having the unprocessed PUF readout exposed externally. This incorporation of the randomness characterization and evaluation processing into one unit reduces the risk of man-in-the-middle and side-channel attacks aimed at the communication between the two areas.

A categorized sample of the collection of over 40 PUF concepts so far suggested [1]
PUF nameMeasurement processRandomness sourceIntrinsic evaluation?Year
Via PUF [4] [5] Fully ElectronicImplicitIntrinsic2015
Delay PUF [6] 2002
SRAM PUF [7] 2007
Metal resistance PUF [8] 2009
Bistable Ring PUF [9] 2011
DRAM PUF [10] 2015
Digital PUF [11] 2016
Oxide Rupture PUF [12] 2018
Coating PUF [13] ExplicitExtrinsic2006
Quantum Electronic PUF [14] 2015
Optical PUF [15] [16] Optical2002
Quantum Optical PUF [17] 2017
RF PUF [18] RF2002
Magnetic PUF [19] MagneticImplicit1994

Electronic-measurement PUFs

Implicit randomness

Via PUF

The Via PUF technology is based on "via" or "contact" formation during the standard CMOS fabrication process. The technology is the outcome of the reverse thinking process. Rather than meeting the design rules, it makes the sizes of Via or Contact be smaller than the requirements in a controlled manner, resulting in unpredictable or stochastic formation of Via or Contact, i.e. 50% probability of making the electrical connection. The technology details are published in 2020 [4] [5] for the first time while the technology is already in mass production in 2015 by ICTK. Few characteristics of Via PUF are followings:

  • Reliability: Thanks to the metallic property, once "via" or "contact" are formed in a structure, they stay there nearly permanently regardless of PVT variation, which means 0% of bit error rate and thus the post processing stages such as error correction code or helper data algorithm are not required. The technology is verified by the JEDEC standard tests and passed the Automotive Electronics Council Q-100 Grade 3 test for automotive applications.
  • Randomness of the Via PUF achieves 0.4972 of Hamming weight closed to the ideal value of 0.5. The technology passed NIST Special Publication 800-92 and NIST SP 800-90B randomness tests.
  • Uniqueness and ‘InbornID’: Uniqueness is an important property of PUF since it would guarantee that one chip ID is always different from other chips. The Via PUF reports 0.4999 of Hamming Distance value closed to the ideal uniqueness of 0.5. The 'InbornID' of the Via PUF stands for on-chip unique ‘inborn’ ID of a silicon chip.
  • Obscurity is one of the great advantages of using the Via PUF technology in IC implementation. The Via or Contact holes of PUF are scattered around all over the chip. No need to form array blocks like the SRAM PUF. Practically impossible to distinguish PUF Vias from regular logic Vias, making IC reverse engineering almost impossible.
  • Standard Manufacturing Process: The Via PUF technology uses standard cell structures from standard digital library with regular core voltage. No high voltage, and so no special circuitry like charge pump. There is no extra mask layer required in the IC manufacturing process.

The Via PUF based Hardware RoT (Root of Trust) chips are currently applied in various markets such as telecommunications, appliances, and IoT devices in the forms of Wifi/BLE modules, smart door locks, IP cameras, IR sensor hub, etc. The technology supports the security functionalities such as anti-counterfeiting, secure boot, secure firmware copy protection, secure firmware update and secure data integrity.

Delay PUF

A delay PUF exploits the random variations in delays of wires and gates on silicon. Given an input challenge, a race condition is set up in the circuit, and two transitions that propagate along different paths are compared to see which comes first. An arbiter, typically implemented as a latch, produces a 1 or a 0, depending on which transition comes first. Many circuits realizations are possible and at least two have been fabricated. When a circuit with the same layout mask is fabricated on different chips, the logic function implemented by the circuit is different for each chip due to the random variations of delays.

A PUF based on a delay loop, i.e., a ring oscillator with logic, in the publication that introduced the PUF acronym and the first integrated PUF of any type. [6] A multiplexor-based PUF has been described, [20] as has a secure processor design using a PUF [21] and a multiplexor-based PUF with an RF interface for use in RFID anti-counterfeiting applications. [22]

SRAM PUF

These PUFs use the randomness in the power-up behavior of standard static random-access memory on a chip as a PUF. The use of SRAM as a PUF was introduced in 2007 simultaneously by researchers at the Philips High Tech Campus and at the University of Massachusetts. [7] [23] [24] Since the SRAM PUF can be connected directly to standard digital circuitry embedded on the same chip, they can be immediately deployed as a hardware block in cryptographic implementations, making them of particular interest for security solutions. SRAM-based PUF technology has been investigated extensively. Several research papers explore SRAM-based PUF technology on topics such as behavior, implementation, or application for anti-counterfeiting purposes. [25] [26] Notable is the implementation of secure secret key storage without storing the key in digital form. [24] [26] [27] SRAM PUF-based cryptographic implementations have been commercialized by Intrinsic ID, [28] a spin-out of Philips, and as of 2019, are available on every technology node from 350 nm down to 7 nm.

Due to deep submicron manufacturing process variations, every transistor in an Integrated Circuit (IC) has slightly different physical properties. These lead to small differences in electronic properties, such as transistor threshold voltages and gain factor. The start-up behavior of an SRAM cell depends on the difference of the threshold voltages of its transistors and other transistor parameters. An SRAM cell has two stable states, which normally represent the zero and one logical states. If the transistors of an SRAM cell were identical, the cell will be perfectly balanced and it will randomly start into one of the two stable states. However, even the smallest differences between transistor parameters will create a cell imbalance and will push the SRAM cell into one of the two stable states with a higher probability than the other state. [29] Given that most SRAM cells have its own preferred state every time they are powered, from an SRAM array of cells a unique and random pattern of zeros and ones can be obtained. This pattern is like a chip’s fingerprint, since it is unique to a particular SRAM and hence to a particular chip.

Post-processing of SRAM PUF

SRAM PUF response is a noisy fingerprint since a small number of the cells, close to equilibrium is unstable. In order to use SRAM PUF reliably as a unique identifier or to extract cryptographic keys, post-processing is required. [30] This can be done by applying error correction techniques, such as ‘helper data algorithms’ [31] or fuzzy extractors. [32] These algorithms perform two main functions: error correction and privacy amplification. This approach allows a device to create a strong device-unique secret key from the SRAM PUF and power down with no secret key present. By using helper data, the exact same key can be regenerated from the SRAM PUF when needed.

Aging of SRAM PUF

An operational IC slowly but gradually changes over time, i.e. it ages. The dominant aging effect in modern ICs that at the same time has a large impact on the noisy behavior of the SRAM PUF is NBTI. Since the NBTI is well understood, there are several ways to counteract the aging tendency. Anti-aging strategies have been developed that cause SRAM PUF to become more reliable over time, without degrading the other PUF quality measures such as security and efficiency. [33]

SRAM PUF in commercial applications

SRAM PUFs were initially used in applications with high security requirements, such as in defense, to protect sensitive government and military systems, and in the banking industry, to secure payment systems and financial transactions. In 2010, NXP started using SRAM PUF technology to secure SmartMX-powered assets against cloning, tampering, theft-of-service and reverse engineering. [34] Since 2011, Microsemi is offering SRAM PUF implementations to add security to secure government and sensitive commercial applications on the company's flash-based devices and development boards. [35] More recent applications include: a secure sensor-based authentication system for the IoT, [36] incorporation in RISC-V-based IoT application processors to secure intelligent, battery-operated sensing devices at the edge, [37] and the replacement of traditional OTP-plus-key-injection approaches to IoT security in high-volume, low-power microcontrollers and crossover processors. [38]

Some SRAM-based security systems in the 2000s refer to "chip identification" rather than the more standard term of "PUF." The research community and industry have now largely embraced the term PUF to describe this space of technology.[ citation needed ]

Butterfly PUF

The Butterfly PUF is based on cross-coupling of two latches or flip-flops. [39] The mechanism being used in this PUF is similar to the one behind the SRAM PUF but has the advantage that it can be implemented on any SRAM FPGA.

Metal resistance PUF

The metal resistance-based PUF derives its entropy from random physical variations in the metal contacts, vias and wires that define the power grid and interconnect of an IC. [8] [40] [41] [42] There are several important advantages to leveraging random resistance variations in the metal resources of an IC including:

  • Temperature and voltage stability: Temperature and voltage (TV) variations represent one of the most significant challenges for PUFs in applications that require re-generation of exactly the same bitstring later in time, e.g., encryption. Metal resistance (unlike transistors) varies linearly with temperature and is independent of voltage. Therefore, metal resistance provides a very high level of robustness to changing environmental conditions.
  • Ubiquity: Metal is (currently) the only conducting material on the chip that is layered, effectively enabling high density, and very compact, PUF entropy sources. Advanced processes create 11 or more metal layers on top of the (x,y) plane of the underlying transistors.
  • Reliability: The wear-out mechanism for metal is electro-migration, which like TV variations, adversely affects the ability of the PUF to reproduce the same bitstring over time. However, the electro-migration process is well understood and can be completely avoided with proper sizing of the metal wires, vias and contacts. Transistor reliability issues, e.g., NBTI (negative-bias temperature instability) and HCI, on the other hand, are more difficult to mitigate.
  • Resiliency: Recent reports have shown that transistor-based PUFs, in particular the SRAM PUF, are subject to cloning. Metal resistance PUFs are not subject to these types of cloning attacks due to the high complexity associated with 'trimming' wires in the clone as a means of matching resistances. Moreover, by adding one or more shielding layers in the thicker upper metal layers that overlay the underlying PUF (which is built using the lower metal layers), front-side probing attacks designed to extract the metal resistances for the clone is extremely difficult or impossible.

Bistable Ring PUF

The Bistable Ring PUF or BR-PUF was introduced by Q. Chen et al. in. [9] [43] The BR-PUF is based on the idea that a ring of even number of inverters has two possible stable states. By duplicating the inverters and adding multiplexers between stages, it is possible to generate exponentially large number of challenge-response pairs from the BR-PUF.

DRAM PUF

Since many computer systems have some form of DRAM on board, DRAMs can be used as an effective system-level PUF. DRAM is also much cheaper than static RAM (SRAM). Thus, DRAM PUFs could be a source of random but reliable data for generating board identifications (chip ID). The advantage of the DRAM PUF is based on the fact that the stand-alone DRAM already present in a system on a chip can be used for generating device-specific signatures without requiring any additional circuitry or hardware. Tehranipoor et al. [10] presented the first DRAM PUF that uses the randomness in the power-up behavior of DRAM cells. Other types of DRAM PUFs include ones based on the data retention of DRAM cells, [44] and on the effects of changing the write and read latency times used in DRAMs. [45] [46]

Digital PUF

Digital PUF [11] overcomes the vulnerability issues in conventional analog silicon PUFs. Unlike the analog PUFs where the fingerprints come from transistors' intrinsic process variation natures, the fingerprints of digital circuit PUFs are extracted from the VLSI interconnect geometrical randomness induced by lithography variations. Such interconnection uncertainty however is incompatible to CMOS VLSI circuits due to issues like short circuit, floating gate voltages etc. for transistors. One solution is to use strongly skewed latches to ensure the stable operating state of each CMOS transistor hence ensuring the circuit itself is immune against environmental and operational variations.

Oxide Rupture PUF

Oxide rupture PUF [12] is a type of PUF benefiting from randomness obtained from inhomogeneous natural gate oxide properties occurring in IC manufacturing process. Along with the truly random, un-predictable and highly stable properties, which is the most ideal source for physical unclonable function. IC design houses can strongly enhance security level by implementing oxide rupture PUF in its IC design, without concerns about the reliability and life time issue and can get rid of the additional costs from complicated ECC (Error Correction Code) circuits. Oxide rupture PUF can extract uniformly-distributed binary bits through amplification and self-feedback mechanism, the random bits are activated upon enrollment, and due to a large entropy bit pool, users are provided the desired flexibility to choose their own key-generation and management approaches. Security level can be upgraded by oxide rupture PUF's intrinsic truly randomness and invisible features.

Explicit randomness

Coating PUF

A coating PUF [13] [47] [48] can be built in the top layer of an integrated circuit (IC). Above a normal IC, a network of metal wires is laid out in a comb shape. The space between and above the comb structure is filled with an opaque material and randomly doped with dielectric particles. Because of the random placement, size and dielectric strength of the particles, the capacitance between each couple of metal wires will be random up to a certain extent. This unique randomness can be used to obtain a unique identifier for the device carrying the Coating PUF. Moreover, the placement of this opaque PUF in the top layer of an IC protects the underlying circuits from being inspected by an attacker, e.g. for reverse-engineering. When an attacker tries to remove (a part of) the coating, the capacitance between the wires is bound to change and the original unique identifier will be destroyed. It was shown how an unclonable RFID tag is built with coating PUFs. [49]

Quantum Electronic PUF

As the size of a system is reduced below the de Broglie wavelength, the effects of quantum confinement become extremely important. The intrinsic randomness within a quantum confinement PUF originates from the compositional and structural non-uniformities on the atomic level. The physical characteristics are dependent on the effects of quantum mechanics at this scale, whilst the quantum mechanics are dictated by the random atomic structure. Cloning this type of structure is practically impossible due to the large number of atoms involved, the uncontrollable nature of processes on the atomic level and the inability to manipulate atoms reliably.

It has been shown that quantum confinement effects can be used to construct a PUF, in devices known as resonant-tunneling diodes. These devices can be produced in standard semiconductor fabrication processes, facilitating mass-production of many devices in parallel. This type of PUF requires atom-level engineering to clone and is the smallest, highest bit density PUF known to date. Furthermore, this type of PUF could be effectively reset by purposely overbiasing the device to cause a local rearrangement of atoms. [14]

Hybrid-measurement PUFs

Implicit randomness

Magnetic PUF

A magnetic PUF exists on a magnetic stripe card. The physical structure of the magnetic media applied to a card is fabricated by blending billions of particles of barium ferrite together in a slurry during the manufacturing process. The particles have many different shapes and sizes. The slurry is applied to a receptor layer. The particles land in a random fashion, much like pouring a handful of wet magnetic sand onto a carrier. To pour the sand to land in exactly the same pattern a second time is physically impossible due to the inexactness of the process, the sheer number of particles, and the random geometry of their shape and size. The randomness introduced during the manufacturing process cannot be controlled. This is a classic example of a PUF using intrinsic randomness.

When the slurry dries, the receptor layer is sliced into strips and applied to plastic cards, but the random pattern on the magnetic stripe remains and cannot be changed. Because of their physically unclonable functions, it is highly improbable that two magnetic stripe cards will ever be identical. Using a standard-sized card, the odds of any two cards having an exact matching magnetic PUF are calculated to be 1 in 900 million.[ citation needed ] Further, because the PUF is magnetic, each card will carry a distinctive, repeatable and readable magnetic signal.

  • Personalizing the magnetic PUF: The personal data encoded on the magnetic stripe contributes another layer of randomness. When the card is encoded with personal identifying information, the odds of two encoded magstripe cards having an identical magnetic signature are approximately 1 in 10 billion.[ citation needed ] The encoded data can be used as a marker to locate significant elements of the PUF. This signature can be digitized and is generally called a magnetic fingerprint. An example of its use is in the Magneprint brand system. [50] [51] [52]
  • Stimulating the magnetic PUF: The magnetic head acts as a stimulus on the PUF and amplifies the random magnetic signal. Because of the complex interaction of the magnetic head, influenced by speed, pressure, direction and acceleration, with the random components of the PUF, each swipe of the head over the magnetic PUF will yield a stochastic, but very distinctive signal. Think of it as a song with thousands of notes. The odds of the same notes recurring in an exact pattern from a single card swiped many times are 1 in 100 million, but overall the melody remains very recognizable.
  • Uses for a magnetic PUF: The stochastic behavior of the PUF in concert with the stimulus of the head makes the magnetic stripe card an excellent tool for dynamic token authentication, forensic identification, key generation, one-time passwords, and digital signatures.

Explicit randomness

Optical PUF

An optical PUF which was termed POWF (physical one-way function) [53] [16] consists of a transparent material that is doped with light scattering particles. When a laser beam shines on the material, a random and unique speckle pattern will arise. The placement of the light scattering particles is an uncontrolled process and the interaction between the laser and the particles is very complex. Therefore, it is very hard to duplicate the optical PUF such that the same speckle pattern will arise, hence the postulation that it is "unclonable".

Quantum Optical PUF

Leveraging the same quantum derived difficulty to clone as the Quantum Electronic PUF, a Quantum PUF operating in the optical regime can be devised. Imperfections created during crystal growth or fabrication lead to spatial variations in the bandgap of 2D materials that can be characterized through photoluminescence measurements. It has been shown that an angle-adjustable transmission filter, simple optics and a CCD camera can capture spatially-dependent photoluminescence to produce complex maps of unique information from 2D monolayers. [17]

RF PUF

The digitally modulated data in modern communication circuits are subjected to device-specific unique analog/RF impairments such as frequency error/offset and I-Q imbalance (in the transmitter), and are typically compensated for at the receiver which rejects these non-idealities. RF-PUF, [54] [55] and RF-DNA [56] [57] [58] utilize those existing non-idealities to distinguish among transmitter instances. RF-PUF does not use any additional hardware at the transmitter and can be used as a stand-alone physical-layer security feature, or for multi-factor authentication, in conjunction with network-layer, transport-layer and application-layer security features.

Related Research Articles

<span class="mw-page-title-main">Computer memory</span> Computer component that stores information for immediate use

Computer memory stores information, such as data and programs, for immediate use in the computer. The term memory is often synonymous with the terms RAM,main memory, or primary storage. Archaic synonyms for main memory include core and store.

<span class="mw-page-title-main">Very-large-scale integration</span> Creating an integrated circuit by combining many transistors into a single chip

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining millions or billions of MOS transistors onto a single chip. VLSI began in the 1970s when MOS integrated circuit chips were developed and then widely adopted, enabling complex semiconductor and telecommunications technologies. The microprocessor and memory chips are VLSI devices.

<span class="mw-page-title-main">CMOS</span> Technology for constructing integrated circuits

Complementary metal–oxide–semiconductor is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips, and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors, data converters, RF circuits, and highly integrated transceivers for many types of communication.

<span class="mw-page-title-main">Static random-access memory</span> Type of computer memory

Static random-access memory is a type of random-access memory (RAM) that uses latching circuitry (flip-flop) to store each bit. SRAM is volatile memory; data is lost when power is removed.

<span class="mw-page-title-main">Dynamic random-access memory</span> Type of computer memory

Dynamic random-access memory is a type of random-access semiconductor memory that stores each bit of data in a memory cell, usually consisting of a tiny capacitor and a transistor, both typically based on metal–oxide–semiconductor (MOS) technology. While most DRAM memory cell designs use a capacitor and transistor, some only use two transistors. In the designs where a capacitor is used, the capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. The electric charge on the capacitors gradually leaks away; without intervention the data on the capacitor would soon be lost. To prevent this, DRAM requires an external memory refresh circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to static random-access memory (SRAM) which does not require data to be refreshed. Unlike flash memory, DRAM is volatile memory, since it loses its data quickly when power is removed. However, DRAM does exhibit limited data remanence.

<span class="mw-page-title-main">Application-specific integrated circuit</span> Integrated circuit customized for a specific task

An application-specific integrated circuit is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficiency video codec. Application-specific standard product chips are intermediate between ASICs and industry standard integrated circuits like the 7400 series or the 4000 series. ASIC chips are typically fabricated using metal–oxide–semiconductor (MOS) technology, as MOS integrated circuit chips.

Magnetoresistive random-access memory (MRAM) is a type of non-volatile random-access memory which stores data in magnetic domains. Developed in the mid-1980s, proponents have argued that magnetoresistive RAM will eventually surpass competing technologies to become a dominant or even universal memory. Currently, memory technologies in use such as flash RAM and DRAM have practical advantages that have so far kept MRAM in a niche role in the market.

Reading is an action performed by computers, to acquire data from a source and place it into their volatile memory for processing. Computers may read information from a variety of sources, such as magnetic storage, the Internet, or audio and video input ports. Reading is one of the core functions of a Turing machine.

Semiconductor memory is a digital electronic semiconductor device used for digital data storage, such as computer memory. It typically refers to devices in which data is stored within metal–oxide–semiconductor (MOS) memory cells on a silicon integrated circuit memory chip. There are numerous different types using different semiconductor technologies. The two main types of random-access memory (RAM) are static RAM (SRAM), which uses several transistors per memory cell, and dynamic RAM (DRAM), which uses a transistor and a MOS capacitor per cell. Non-volatile memory uses floating-gate memory cells, which consist of a single floating-gate transistor per cell.

<span class="mw-page-title-main">Ferroelectric RAM</span> Novel type of computer memory

Ferroelectric RAM is a random-access memory similar in construction to DRAM but using a ferroelectric layer instead of a dielectric layer to achieve non-volatility. FeRAM is one of a growing number of alternative non-volatile random-access memory technologies that offer the same functionality as flash memory. An FeRAM chip contains a thin film of ferroelectric material, often lead zirconate titanate, commonly referred to as PZT. The atoms in the PZT layer change polarity in an electric field, thereby producing a power-efficient binary switch. However, the most important aspect of the PZT is that it is not affected by power disruption or magnetic interference, making FeRAM a reliable nonvolatile memory.

<span class="mw-page-title-main">Integrated circuit design</span> Engineering process for electronic hardware

Integrated circuit design, semiconductor design, chip design or IC design, is a sub-field of electronics engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized electronic components built into an electrical network on a monolithic semiconductor substrate by photolithography.

Memory refresh is a process of periodically reading information from an area of computer memory and immediately rewriting the read information to the same area without modification, for the purpose of preserving the information. Memory refresh is a background maintenance process required during the operation of semiconductor dynamic random-access memory (DRAM), the most widely used type of computer memory, and in fact is the defining characteristic of this class of memory.

<span class="mw-page-title-main">Physical unclonable function</span> Unreproducible object used in digital security

A physical unclonable function, or PUF, is a physical object whose operation cannot be reproduced ("cloned") in physical way, that for a given input and conditions (challenge), provides a physically defined "digital fingerprint" output (response). that serves as a unique identifier, most often for a semiconductor device such as a microprocessor. PUFs are often based on unique physical variations occurring naturally during semiconductor manufacturing. A PUF is a physical entity embodied in a physical structure. PUFs are implemented in integrated circuits, including FPGAs, and can be used in applications with high-security requirements, more specifically cryptography, Internet of Things (IOT) devices and privacy protection.

A three-dimensional integrated circuit is a MOS integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits in microelectronics and nanoelectronics.

<span class="mw-page-title-main">Read-only memory</span> Electronic memory that cannot be changed

Read-only memory (ROM) is a type of non-volatile memory used in computers and other electronic devices. Data stored in ROM cannot be electronically modified after the manufacture of the memory device. Read-only memory is useful for storing software that is rarely changed during the life of the system, also known as firmware. Software applications, such as video games, for programmable devices can be distributed as plug-in cartridges containing ROM.

<span class="mw-page-title-main">Random-access memory</span> Form of computer data storage

Random-access memory is a form of electronic computer memory that can be read and changed in any order, typically used to store working data and machine code. A random-access memory device allows data items to be read or written in almost the same amount of time irrespective of the physical location of data inside the memory, in contrast with other direct-access data storage media, where the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.

A Hardware Trojan (HT) is a malicious modification of the circuitry of an integrated circuit. A hardware Trojan is completely characterized by its physical representation and its behavior. The payload of an HT is the entire activity that the Trojan executes when it is triggered. In general, Trojans try to bypass or disable the security fence of a system: for example, leaking confidential information by radio emission. HTs also could disable, damage or destroy the entire chip or components of it.

<span class="mw-page-title-main">Memory cell (computing)</span> Part of computer memory

The memory cell is the fundamental building block of computer memory. The memory cell is an electronic circuit that stores one bit of binary information and it must be set to store a logic 1 and reset to store a logic 0. Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.

Hardware security is a discipline originated from the cryptographic engineering and involves hardware design, access control, secure multi-party computation, secure key storage, ensuring code authenticity, measures to ensure that the supply chain that built the product is secure among other things.

In integrated circuits (ICs), interconnects are structures that connect two or more circuit elements together electrically. The design and layout of interconnects on an IC is vital to its proper function, performance, power efficiency, reliability, and fabrication yield. The material interconnects are made from depends on many factors. Chemical and mechanical compatibility with the semiconductor substrate and the dielectric between the levels of interconnect is necessary, otherwise barrier layers are needed. Suitability for fabrication is also required; some chemistries and processes prevent the integration of materials and unit processes into a larger technology (recipe) for IC fabrication. In fabrication, interconnects are formed during the back-end-of-line after the fabrication of the transistors on the substrate.

References

  1. 1 2 McGrath, Thomas; Bagci, Ibrahim E.; Wang, Zhiming M.; Roedig, Utz; Young, Robert J. (2019). "A PUF taxonomy". Applied Physics Reviews. 6 (11303): 011303. Bibcode:2019ApPRv...6a1303M. doi: 10.1063/1.5079407 . S2CID   86448102.
  2. ↑ Maes, R. (2013). Physically unclonable functions: Concept and constructions. Springer. pp. 11–48.
  3. ↑ Verbauwhede, I.; Maes, R. (2011). "Physically unclonable functions: Manufacturing variability as an unclonable device identifier" (PDF). Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI): 455–460.
  4. 1 2 D. J. Jeon, et al., A Physical Unclonable Function with Bit Error Rate < 2.3x10-8 based on Contact Formation Probability without Error Correction Code, IEEE J. Solid-State Circuits, vol. 55, No. 3, pp. 805-816, March 2020.
  5. 1 2 2020 GSA Forum "Via PUF Technology as a Root of Trust in IoT Supply Chain" https://www.gsaglobal.org/forums/via-puf-technology-as-a-root-of-trust-in-iot-supply-chain
  6. 1 2 Gassend, B.; Clarke, D.; Dijk, M. v.; Devadas, S. (2002). "Silicon physical random functions". Proceedings of the 9th ACM conference on Computer and communications security. pp. 148–160. CiteSeerX   10.1.1.297.5196 . doi:10.1145/586110.586132. ISBN   1581136129. S2CID   1788365.
  7. 1 2 Jorge Guajardo, Sandeep S. Kumar, Geert-Jan Schrijen, Pim Tuyls, "FPGA Intrinsic PUFs and Their Use for IP Protection", Workshop on Cryptographic Hardware and Embedded Systems (CHES), Sep 10-13, 2007, Vienne, Austria
  8. 1 2 Helinski, R.; Acharyya, D.; Plusquellic, J. (2009). "A physical unclonable function defined using power distribution system equivalent resistance variations". Proceedings of the 46th Annual Design Automation Conference. pp. 676–681. doi:10.1145/1629911.1630089. ISBN   9781605584973. S2CID   2537549.
  9. 1 2 Chen, Qingqing; Csaba, Gyorgy; Lugli, Paolo; Schlichtmann, Ulf; Ruhrmair, Ulrich (2011). "The Bistable Ring PUF: A new architecture for strong Physical Unclonable Functions". 2011 IEEE International Symposium on Hardware-Oriented Security and Trust. pp. 134–141. doi:10.1109/HST.2011.5955011. ISBN   978-1-4577-1059-9. S2CID   8067138.
  10. 1 2 Tehranipoor, F.; Karimian, N.; Xiao, K.; Chandy, J. A. (2015). "DRAM based Intrinsic Physical Unclonable Functions for System Level Security". Proceedings of the 25th edition on Great Lakes Symposium on VLSI. pp. 15–20. doi:10.1145/2742060.2742069. ISBN   9781450334747. S2CID   2287478.
  11. 1 2 Miao, Jin; Li, Meng; Roy, Subhendu; Yu, Bei. "LRR-DPUF: Learning resilient and reliable digital physical unclonable function". Iccad 2016.
  12. 1 2 2018 ISSCC "A PUF scheme using competing oxide rupture with bit error rate approaching zero" https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8310218&tag=1
  13. 1 2 Pim Tuyls, Geert-Jan Schrijen, Boris Skoric, Jan van Geloven, Nynke Verhaegh and Rob Wolters: "Read-proof hardware from protective coatings", CHES 2006, pp 369–383.
  14. 1 2 Roberts, J.; Bagci, I. E.; Zawawi, M. A. M.; Sexton, J.; Hulbert, N.; Noori, Y. J.; Young, M. P.; Woodhead, C. S.; Missous, M. (2015-11-10). "Using Quantum Confinement to Uniquely Identify Devices". Scientific Reports. 5: 16456. arXiv: 1502.06523 . Bibcode:2015NatSR...516456R. doi:10.1038/srep16456. PMC   4639737 . PMID   26553435.
  15. ↑ R. Pappu, "Physical One-Way Functions", PhD Thesis, MIT, 2001. Physical One-Way Functions.
  16. 1 2 Pappu, R.; Recht, B.; Taylor, J.; Gershenfeld, N. (2002). "Physical One-Way functions" (PDF). Science. 297 (5589): 2026–2030. Bibcode:2002Sci...297.2026P. doi:10.1126/science.1074376. hdl: 1721.1/45499 . PMID   12242435.
  17. 1 2 Cao, Yameng; Robson, Alexander J.; Alharbi, Abdullah; Roberts, Jonathan; Woodhead, Christopher Stephen; Noori, Yasir Jamal; Gavito, Ramon Bernardo; Shahrjerdi, Davood; Roedig, Utz (2017). "Optical identification using imperfections in 2D materials". 2D Materials. 4 (4): 045021. arXiv: 1706.07949 . Bibcode:2017TDM.....4d5021C. doi:10.1088/2053-1583/aa8b4d. ISSN   2053-1583. S2CID   35147364.
  18. ↑ Dejean, G.; Kirovski, D. (2007). "RF-DNA: Radio-Frequency Certificates of Authenticity" (PDF). Cryptographic Hardware and Embedded Systems - CHES 2007. Lecture Notes in Computer Science. Vol. 4727. pp. 346–363. doi:10.1007/978-3-540-74735-2_24. ISBN   978-3-540-74734-5.
  19. ↑ Indeck, R. S.; Muller, M. W. (1994). Method and apparatus for fingerprinting magnetic media (PDF). United States of America.{{cite book}}: CS1 maint: location missing publisher (link)
  20. ↑ Lim, D.; Lee, J-W.; Gassend, B.; Suh, E.; Devadas, S. (2005). "Extracting Secret Keys from Integrated Circuits". IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13 (10): 1200–1205. doi:10.1109/tvlsi.2005.859470. S2CID   11325408.
  21. ↑ Suh, G. E.; O'Donnell, C. W.; Devadas, S. (2007). "Aegis: A Single-Chip secure processor". IEEE Design and Test of Computers. 24 (6): 570–580. doi:10.1109/MDT.2007.179. hdl: 1721.1/34469 .
  22. ↑ S. Devadas, V. Khandelwal, S. Paral, R. Sowell, E. Suh, T. Ziola, Design and Implementation of `Unclonable' RFID ICs for Anti-Counterfeiting and Security Applications, RFID World 2008, March 2008
  23. ↑ Holcomb, Daniel; Wayne Burleson; Kevin Fu (July 2007). "Initial SRAM State as a Fingerprint and Source of True Random Numbers for RFID Tags" (PDF). Proceedings of the Conference on RFID Security. Malaga, Spain.
  24. 1 2 Jorge Guajardo, Sandeep S. Kumar, Geert-Jan Schrijen, Pim Tuyls, "Physical Unclonable Functions and Public-Key Crypto for FPGA IP Protection", International Conference on Field Programmable Logic and Applications (FPL), Aug 27-29, 2007, Amsterdam, the Netherlands.
  25. ↑ Holcomb, Daniel; Wayne Burleson; Kevin Fu (September 2009). "Power-up SRAM State as an Identifying Fingerprint and Source of True Random Numbers" (PDF). IEEE Transactions on Computers. 58 (9): 1198–1210. CiteSeerX   10.1.1.164.6432 . doi:10.1109/tc.2008.212. S2CID   60072.
  26. 1 2 Christoph Böhm, Maximilian Hofer, "Using SRAMs as Physical Unclonable Functions", Austrochip – Workshop on Microelectronics, Oct 7, 2009, Graz, Austria
  27. ↑ Georgios Selimis, Mario Konijnenburg, Maryam Ashouei, Jos Huisken, Harmke de Groot, Vincent van der Leest, Geert-Jan Schrijen, Marten van Hulst, Pim Tuyls, "Evaluation of 90nm 6T-SRAM as Physical Unclonable Function for secure key generation in wireless sensor nodes", IEEE International Symposium on Circuits and Systems (ISCAS), 2011
  28. ↑ Intrinsic ID company website
  29. ↑ Torrens, Gabriel; Alheyasat, Abdel; Alorda, Bartomeu; Bota, Sebastià A. (2022-01-02). "SRAM-Based PUF Reliability Prediction Using Cell-Imbalance Characterization in the State Space Diagram". Electronics. 11 (1): 135. doi: 10.3390/electronics11010135 . hdl: 20.500.13003/19829 . ISSN   2079-9292.
  30. ↑ Tuyls, Pim; Šcorić, Boris; Kevenaar, Tom (2007). Security with Noisy Data: Private Biometics, Secure Key Storage and Anti-counterfeiting. Springer. doi:10.1007/978-1-84628-984-2. ISBN   978-184628-983-5.
  31. ↑ J.-P. Linnartz and P. Tuyls, “New shielding functions to enhance privacy and prevent misuse of biometric templates,” in International Conference on Audio and Video-based Biometric Person Authentication (AVBPA’03), ser. LNCS, J. Kittler and M. S. Nixon, Eds., vol. 2688. Heidelberg: Springer-Verlag, 2003, pp. 393–402.
  32. ↑ X. Boyen, “Reusable cryptographic fuzzy extractors,” in ACM Conference on Computer and Communications Security (CCS’04). New York, NY, USA: ACM, 2004, pp. 82–91. AND Y. Dodis, L. Reyzin, and A. Smith, “Fuzzy extractors: How to generate strong keys from biometrics and other noisy data,” in EUROCRYPT’04, ser. LNCS, C. Cachin and J. Camenisch, Eds., vol. 3027. Heidelberg: Springer-Verlag, 2004, pp. 523– 540.
  33. ↑ R. Maes and V. van der Leest, "Countering the effects of silicon aging on SRAM PUFs", Proc. IEEE Int. Symp. Hardw.-Oriented Secur. Trust (HOST 2014), pp. 148-153 available at https://www.intrinsic-id.com/wp-content/uploads/2017/05/PUF_aging.pdf
  34. ↑ NXP and Intrinsic-ID to raise smart chip security, EETimes, 2010
  35. ↑ Microsemi to offer Intrinsic-ID security in FPGAs and systems-on-chip for sensitive military applications, Military & Aerospace Electronics, August 2011
  36. ↑ Intrinsic ID to showcase TrustedSensor IoT Security Solution at InvenSense Developers Conference, Press Release, September 2015
  37. ↑ GreenWaves Technologies Licenses Intrinsic ID Hardware Root of Trust for RISC-V AI Application Processor, Press Release, September 2018
  38. ↑ Intrinsic ID’s Scalable Hardware Root of Trust IP Delivers Device Authentication for IoT Security in NXP LPC Microcontroller Portfolio, Press Release, March 2019
  39. ↑ S. Kumar, J. Guajardo, R. Maes, G.J. Schrijen qnd P. Tuyls, The Butterfly PUF: Protecting IP on every FPGA, In IEEE International Workshop on Hardware Oriented Security and Trust, Anaheim 2008.
  40. ↑ R. Helinski, D. Acharyya, J. Plusquellic, Quality Metric Evaluation of a Physical Unclonable Function Derived from an IC's Power Distribution System, Design Automation Conference, pp. 240–243, 2010. http://www.ece.unm.edu/~jimp/pubs/dac2010_FINAL.pdf
  41. ↑ J. Ju, R. Chakraborty, R. Rad, J. Plusquellic, Bit String Analysis of Physical Unclonable Functions based on Resistance Variations in Metals and Transistors, Symposium on Hardware-Oriented Security and Trust (HOST), 2012, pp. 13–20. http://www.ece.unm.edu/~jimp/pubs/PG_TG_PUF_ALL_FINAL.pdf
  42. ↑ J. Ju, R. Chakraborty, C. Lamech and J. Plusquellic, Stability Analysis of a Physical Unclonable Function based on Metal Resistance Variations, accepted Symposium on Hardware-Oriented Security and Trust (HOST), 2013. http://www.ece.unm.edu/~jimp/pubs/HOST2013_PGPUF_Temperature_wVDC_FINAL_VERSION.pdf
  43. ↑ Qingqing Chen, et al. Characterization of the bistable ring PUF. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012. IEEE, 2012. pp. 1459–1462. [ permanent dead link ]
  44. ↑ Xiong, W.; Schaller, A.; Anagnostopoulos, N.A.; Saleem, M.U.; Gabmeyer, S.; Katzenbeisser, S.; Szefer, J. (2016). "Run-Time Accessible DRAM PUFs in Commodity Devices". In Gierlichs, B.; Poschmann, A. (eds.). Cryptographic Hardware and Embedded Systems – CHES 2016. Lecture Notes in Computer Science. Vol. 9813. Springer. pp. 100–110. doi:10.1007/978-3-662-53140-2_21. ISBN   978-3-662-53140-2.
  45. ↑ Kim, J. S.; Patel, M.; Hassan, H.; Mutlu, O. (2018). "The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices". 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA). pp. 194–207. doi:10.1109/HPCA.2018.00026. ISBN   978-1-5386-3659-6. S2CID   4562667.
  46. ↑ Bahar Talukder, B. M. S.; Ray, B.; Forte, D.; Rahman, M. T. (2019). "PreLatPUF: Exploiting DRAM Latency Variations for Generating Robust Device Signatures". IEEE Access. 7: 81106–81120. arXiv: 1808.02584 . Bibcode:2019IEEEA...781106B. doi: 10.1109/ACCESS.2019.2923174 . ISSN   2169-3536. S2CID   51940311.
  47. ↑ Skoric, B.; Maubach, S.; Kevenaar, T.; Tuyls, P. (2006). "Information-theoretic analysis of capacitive physical unclonable functions" (PDF). J. Appl. Phys. 100 (2): 024902–024902–11. Bibcode:2006JAP...100b4902S. doi:10.1063/1.2209532.
  48. ↑ B. Skoric, G.-J. Schrijen, W. Ophey, R. Wolters, N. Verhaegh, and J. van Geloven. Experimental hardware for coating PUFs and optical PUFs. In P. Tuyls, B. Skoric, and T. Kevenaar, editors, Security with Noisy Data – On Private Biometrics, Secure Key Storage and Anti-Counterfeiting, pages 255-268. Springer London, 2008. doi : 10.1007/978-1-84628-984-2_15
  49. ↑ Pim Tuyls, Lejla Batina. RFID-Tags for Anti-counterfeiting. CT-RSA, 2006, pp. 115–131
  50. ↑ Magneprint - Electrical Engineers, Physicists Design System to Combat Credit Card Fraud Archived 2013-11-01 at the Wayback Machine . Aip.org (2005-02-01). Retrieved on 2013-10-30.
  51. ↑ Tony Fitzpatrick, Nov. 11, 2004, "Magneprint technology licensed to TRAX Systems, Inc." http://news-info.wustl.edu/tips/page/normal/4159.html
  52. ↑ Patrick L. Thimangu, January 7, 2005, "Washington U. cashing in with MagnePrint licensing," St. Louis Business Journal http://www.bizjournals.com/stlouis/stories/2005/01/10/story7.html?jst=s_cn_hl
  53. ↑ R. Pappu, "Physical One-Way Functions", PhD Thesis, MIT, 2001. Physical One-Way Functions.
  54. ↑ [B. Chatterjee, D. Das and S. Sen, "RF-PUF: IoT security enhancement through authentication of wireless nodes using in-situ machine learning," 2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, 2018, pp. 205-208. doi : 10.1109/HST.2018.8383916]
  55. ↑ [B. Chatterjee, D. Das, S. Maity and S. Sen, "RF-PUF: Enhancing IoT Security through Authentication of Wireless Nodes using In-situ Machine Learning," in IEEE Internet of Things Journal. doi : 10.1109/JIOT.2018.2849324]
  56. ↑ [D. Kirovski and G. DeJean, "Identifying RF-DNA instances via phase differences," 2009 IEEE Antennas and Propagation Society International Symposium, Charleston, SC, 2009, pp. 1-4. doi : 10.1109/APS.2009.5171790]
  57. ↑ [M. D. Williams, M. A. Temple and D. R. Reising, "Augmenting Bit-Level Network Security Using Physical Layer RF-DNA Fingerprinting," 2010 IEEE Global Telecommunications Conference GLOBECOM 2010, Miami, FL, 2010, pp. 1-6. doi : 10.1109/GLOCOM.2010.5683789]
  58. ↑ [M. W. Lukacs, A. J. Zeqolari, P. J. Collins and M. A. Temple, "“RF-DNA” Fingerprinting for Antenna Classification," in IEEE Antennas and Wireless Propagation Letters, vol. 14, pp. 1455-1458, 2015. doi : 10.1109/LAWP.2015.2411608]
This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.