List of Xilinx FPGAs

This article contains general information about field-programmable gate array (FPGA) devices from AMD Xilinx, based on official specifications.

Terminology

The fields in the table listed below describe the following:

• Model – The marketing name for the device, assigned by Xilinx.
• Launch – Date when the product was announced.
• Sub-models – Some FPGA models have multiple sub-models.
• Flip-Flops (K) – The number of flip-flops embedded within the FPGA fabric.
• LUTs (K) – The number of lookup tables embedded within the FPGA fabric.
• DSP Slices – The number of digital signal processor slices embedded within the FPGA fabric.
• Peak DSP Performance (GMAC/s) – The maximum number of multiply-accumulate operations per second that can be performed by the digital signal processors that are embedded within the FPGA fabric. This is a theoretical best-case number.
• PCIe – Bus by which the device is attached to an external system.
• Max Distributed RAM (Mb) – Random Access Memory within the LUTs. ^[1]
• Total Block RAM (Mb) – On-chip RAM that is not integrated within the LUTs.
• UltraRAM (Mb) – An additional block of RAM that was introduced with the Zynq UltraScale+ FPGA line. UltraRAM can be powered down for extended periods of time. ^[2]

Model naming

The model name of most devices has some indication of its size, but the exact scheme used has varied over time:

• The first Xilinx device, the XC2064, is named after the 64 CLBs it contains
• After that, Xilinx started including a rough approximation of device capacity in equivalent gate count (which is measured by synthesizing a large benchmark design corpus to both a standard gate library and to a given FPGA device, then deriving an approximate conversion factor from that):
  • XC2018 and all XC3000 devices use the gate count divided by 100 (ie. XC3020 is considered a rough equivalent of 2000 gates) ^[3]
  • XC4000, XC5200, XC6200, Spartan, Spartan-II, Spartan-3 (all kinds), Virtex, and Virtex-II (except for Virtex-II Pro) devices use the gate count divided by 1000 (ie. XC4003 is considered roughly equivalent to 3000 gates, XC3S5000 is considered roughly equivalent to 5 million gates). However, the device families differ in whether they use the low bound, average, or high bound of the conversion factor for the model name (eg. XC4003 uses the average of the estimated 2000-5000 gate range listed in the datasheet, while the functionally identical XCS05 uses the high bound of this range).
• Virtex-II Pro and Virtex-4 devices instead started using an "equivalent logic cells" metric divided by 1000 (XC4VLX60 is considered to be an equivalent of 60000 logic cells). The logic cell is, nominally, a simple 4-input LUT paired with a flip-flop. The logic count is obtained by multiplying the LUT count of the device by an arbitrary effectiveness factor of 1.125 to account for the extra capacity of the hard CLB logic compared to a bare LUT. ^[4]
• Virtex-5/6, Spartan-6, and 7 Series (not including Zynq-7000) continue using the same metric, but the effectiveness factor has been updated to 1.6, because of the upgrade from 4-input LUTs to 6-input LUTs.
• UltraScale devices initially used the same "equivalent logic cells" metric, but divided by 10000 for the model name (ie. XCVU440 is considered to be equivalent to 4400000 logic cells), and with the effectiveness factor updated to 1.75 because of CLB upgrades. However, for marketing reasons, later versions of UltraScale data sheets instead started measuring device capacity in a new metric called "system logic cells", using an inflated conversion factor of 2.1875. This makes the model names seemingly unrelated to any device capacity measurements listed in the current data sheets. ^[5]
• Zynq-7000, UltraScale+, and Versal devices abandon the idea of directly embedding logic capacity in the model name, assigning the names more or less arbitrarily.

Series overview

Generation	Family	Launch	Process	Internal operating voltage	Notes
XC2000	XC2000	1985	2000nm [6]	5V	The original FPGA family. This and a few following generations were originally called LCA (Logic Cell Array) devices, but later FPGA gradually became the preferred term.
	XC2000L	1993 [7]		3.3V	Low voltage version of XC2000
XC3000	XC3000	1988	1200nm [6]	5V	Improved logic cell, adds intra-FPGA tri-state bus support
	XC3000A	1993	800nm [3]		XC3000 with more functionality
	XC3000L	1993		3.3V	Low voltage version of XC3000A
	XC3100	1992	800nm [8]	5V	Faster version of XC3000
	XC3100A	1994 [9]	500nm		Faster version of XC3000A
	XC3100L	1995 [10]		3.3V	Faster version of XC3000L
XC4000	XC4000	1991		5V	Improved logic cell, distributed RAM support, features carry chains and JTAG support
	XC4000A	1991		5V	XC4000 with fewer routing resources, small chips
	XC4000D	1994 [11]		5V	Same as XC4000, but with non-functional RAM
	XC4000H	1993		5V	XC4000 with more, but less functional, IO cells (for higher pin count)
	XC4000E	1995 [12]	500nm [13]	5V	XC4000 upgrade with more functionality
	XC4000L	1995 [10]		3.3V	Low voltage version of XC4000E
	XC4000EX	1996 [14]	500nm	5V	XC4000E upgrade with more routing resources, for larger devices
	XC4000XL	1997	350nm [15]	3.3V	Low voltage version of XC4000EX
	XC4000XLA	1998 [16]	350nm, [16] 250nm [15]	3.3V	XC4000XL upgrade with more functionality
	XC4000XV	1998	250nm [15]	2.5V	XC4000XLA variant with more routing resources (for large chips)
	Spartan	1998	500nm, 350nm [17]	5V	Functionally identical to XC4000E, rebranded as low-end part
	Spartan XL	1998 [16]	350nm, [16] 250nm [17]	3.3V	Spartan upgrade with more functionality
XC5200	XC5200	1994	600nm	5V	A low end FPGA family with bare bones logic cells
	XC5200L		500nm	3.3V	Low voltage version of XC5200
XC6200		1995 [12]	650nm	5V	An unusual FPGA based on simple logic cells (not LUTs), meant to be used alongside a CPU and optimized for on-the-fly reconfiguration. The only FPGA to have a fully documented configuration format by Xilinx.
XC8100		1995 [12]		5V or 3.3V	A very unusual sea-of-gates FPGA, using one-time-programmable antifuse storage for the configuration (instead of RAM). Quickly discontinued in 1996. [18]
Virtex	Virtex	1998 [19]	220nm [13]	2.5V	Improved LUT4-based logic cell, first Xilinx FPGA family to feature DLLs and block RAM
	Spartan-II	2000			Identical to Virtex, marketed as low-end part
	Virtex E	1999	180nm	1.8V	Virtex upgrade with more block RAM, more DLLs, and improved IO cells (with differential IO support)
	Virtex EM	2000			Like Virtex E, but with more block RAM
	Spartan-IIE	2001 [20]			Identical to Virtex E, but with some blocks disabled
Virtex-II	Virtex-II	2001	150nm	1.5V	First Xilinx FPGA family to feature partial reconfiguration and hard multipliers, has DDR input/output support, DLLs have been replaced by much more functional DCMs
	Virtex-II Pro	2002	130nm [21]	1.2V	Virtex-II upgrade featuring first-generation multi-gigabit transceivers (3.125 Gbit/s, marketed as RocketIO™) and embedded PPC405 cores
	Virtex-II Pro X	2003 [22]			Virtex-II Pro with multi-gigabit transceiver upgrade (RocketIO X, 6.25 Gbit/s)
Spartan-3	Spartan-3	2003	90nm [17]	1.2V	A low-end, simplified version of Virtex-II
	Spartan-3E	2004 [23]			Spartan-3 upgrade with improved hard multipliers and DCMs, but fewer IO cells
	Spartan-3A	2006			Spartan-3E upgrade with improved block RAM (featuring byte enables) and IO cells
	Spartan-3AN	2007			Spartan-3A version with integrated SPI flash (as a separate die within the same package), requiring no external bitstream storage
	Spartan-3A DSP				Spartan-3A upgrade with new DSP cells (based on Virtex-5 but simplified) replacing the simplistic hard multipliers
Virtex-4		2004	90nm	1.2V	Introduced DSP cells replacing the simple hard multipliers, added simple serdes functionality to all IO cells, improved partial reconfiguration support
	Virtex-4 LX				The base "logic optimized" version
	Virtex-4 SX				DSP-optimized version of Virtex-4: identical functionality to LX, but with much higher DSP-to-logic ratio
	Virtex-4 FX				Virtex-4 with embedded hard PPC405 cores, Ethernet MAC blocks, and multi-gigabit transceivers (6.5 Gbit/s)
Virtex-5		2006	65nm	1.0V	Introduced new LUT6-based logic cells, new block RAM cells (36kbit, splittable to 2×18kbit), new DSP cells; added new PLL blocks in addition to DCM blocks
	Virtex-5 LX				The base "logic optimized" version
	Virtex-5 LXT				Adds multi-gigabit transceiver support on top of LX (RocketIO GTP transceivers, 3.75 Gbit/s); also adds hard PCI Express (Gen1 ×8) and gigabit Ethernet MAC blocks
	Virtex-5 SXT				DSP-optimized version of Virtex-5: identical functionality to LXT, but with much higher DSP-to-logic ratio
	Virtex-5 FXT				Virtex-5 with GTX transceivers (6.5 Gbit/s) and hard PPC440 cores
	Virtex-5 TXT	2009			Transceiver-optimized version of Virtex-5: has large amount of GTX transceivers (no PPC cores)
Virtex-6		2009	40nm	0.9V or 1.0V	Replaces DCM blocks with MMCM blocks (which are an improved version of the existing PLL blocks), minor improvements to logic, DSP, block RAM, and IO cells
	Virtex-6 LX				The base "logic optimized" version
	Virtex-6 LXT				Adds multi-gigabit transceiver support on top of LX (GTX transceivers, up to 6.6 Gbit/s); also adds hard PCI Express (Gen2 ×8) and gigabit Ethernet MAC blocks
	Virtex-6 SXT				DSP-optimized version of Virtex-6; identical functionality to LXT, but with much higher DSP-to-logic ratio
	Virtex-6 HXT				Transceiver-optimized version of Virtex-6: replaces GTX transceivers with GTH transceivers (11.2 Gb/s)
	Virtex-6 CXT				Identical to LXT, but with some transceivers and hard PCI Express / Ethernet MAC blocks disabled
Spartan-6	Spartan-6 LX	2009	45nm	1.0V or 1.2V	A low-end family built from an amalgamation of Spartan-3A and Virtex-6 features; has a LUT6-based logic cell, slightly improved Spartan-3A DSP cell, 18kbit block RAMs (splittable into 2×9kbit), improved DCM blocks, PLL blocks, IO blocks with serdes support; also has a new hard memory controller block
	Spartan-6 LXT				Spartan-6 version with multi-gigabit transceivers (GTP, 3.2 Gbit/s) and hard PCI Express (Gen 1 ×1) block
7 Series		2010	28nm	0.9V, 0.95V, or 1.0V	A successor to the Virtex-6 family, with several separately-marketed sub-families that are made from essentially identical cells with a few exceptions; the IO cells have been split into two variants: HR (high range, 3.3V capable cells) and HP (high performance, 1.8V capable cells with DCI functionality)
	Spartan 7	2017			Low-end logic-optimized parts, feature HRIO and no special blocks; several parts are identical to Artix parts with transceivers disabled
	Artix-7	2010			Low-end parts, feature HRIO, GTP transceivers (6.6 Gbit/s), PCI-Express hard block (Gen 2.1 ×4)
	Kintex-7	2010			Middle-end parts, feature HRIO and sometimes HPIO, GTX transceivers (12.5 Gbit/s), PCI-Express hard block (Gen 2.1 ×8)
	Virtex-7	2010			High-end parts, feature HPIO and sometimes HRIO, GTX or GTH transceivers (13.1 Gbit/s), PCI-Express hard block (Gen 2.1 ×8 or Gen 3 ×8)
	Virtex-7 3D	2011			First FPGA made of multiple die in one package, using a special interposer die for very fast and wide inter-die interconnect, essentially presenting as a single unified device made of several "super logic regions" (SLRs)
	Virtex-7 HT	2012			Virtex-7 3D version that also adds special ultra-high-speed GTZ transceivers (28.05 Gbit/s) via a separate die in the same package
	Zynq-7000	2011			An ARM Cortex-A9 based system on a chip integrated with an Artix-7 or a Kintex-7 FPGA on a single die
UltraScale		2013 [24]	20nm	0.9V, 0.95V, or 1.0V	A successor to 7 Series focused on scalability; features a new distributed clock distribution system as well as upgraded logic, DSP, and block RAM cells; hard blocks include the GTH transceivers (16.3 Gbit/s), GTY transceivers (30.5 Gbit/s), PCI Express (Gen3 ×8) blocks, 100G Ethernet MAC, 150G Interlaken blocks
	Kintex UltraScale	2013			Middle-end parts
	Virtex UltraScale	2014			High-end parts
UltraScale+		2015	16nm	0.72V, 0.85V, or 0.9V	An UltraScale upgrade with faster GTY transceivers (32.75 Gbit/s) and improved hard blocks (PCI Express Gen3 ×16 or Gen4 ×8); HR IO is gone and replaced with simpler HD (High Density) IO; some parts feature new UltraRAM (288kbit RAM) blocks
	Artix UltraScale+	2021			Low-end parts
	Kintex UltraScale+	2015			Middle-end parts
	Virtex UltraScale+	2016			High-end parts
	Virtex UltraScale+ 58G				Features new GTM transceivers (58 Gbit/s PAM4)
	Virtex UltraScale+ HBM				Features High Bandwidth Memory within the same package and an integrated hard memory controller inside the FPGA die
	Zynq UltraScale+ MPSoC	2015			An ARM Cortex-A53 based system on a chip integrated with a Kintex UltraScale+ FPGA on the same die
	Zynq UltraScale+ RFSoC	2017			Like the MPSoC, but adds RF-DAC and RF-ADC blocks for high-speed radios (5G technology)
	Alveo	2018			Alveo is a series of accelerator boards that are built on UltraScale+-series FPGAs that are identical to some Kintex/Virtex/Zynq devices, but are nominally considered to be distinct chip models
Versal		2019	7nm	0.7V, 0.8V, or 0.88V	An ARM Cortex-A72 based system on a chip integrated with a new version of FPGA fabric (with new logic, DSP, and block RAM cells), hard DDR memory controllers, and a network-on-chip (NoC) connecting all of the parts together
	Versal Prime	2019			The base Versal parts
	Versal AI Core	2019			Features the AI engine cores
	Versal Premium				Features high-bandwidth versions of the hard blocks
	Versal AI Edge				Lower-end version of AI Core
	Versal HBM				Features HBM memory

Note: The process information for early FPGA devices (before Virtex) may be inaccurate, due to the devices being subject to die shrink without changing the model name — the process listed above may not be the only process in which a given device has been manufactured.

Early FPGA devices

XC2000

The XC2000 devices have the following user-programmable blocks: ^[25]

• CLBs (Configurable Logic Blocks): each CLB consists of two 3-input LUTs, a hard multiplexer combining LUT outputs (which can be used to combine them to a single 4-input LUT, among other things) and one flip-flop (with asynchronous set and reset capabilities)
• User I/O blocks: each user I/O pin is associated with an I/O block, which consists of an input buffer, an input flip-flop, and a tri-state output buffer
• One crystal oscillator amplifier
• Two global clock buffers

Model	CLBs	User I/O (max)
XC2064, XC2064L	64 (8×8)	58
XC2018, XC2018L	100 (10×10)	74

Note: the available user I/O amount varies with chip packaging.

XC3000

The XC3000 devices have the following user-programmable blocks: ^[26]

• CLBs (Configurable Logic Blocks): each CLB consists of two 4-input LUTs, a hard multiplexer combining LUT outputs (which can be used to combine them to a single 5-input LUT, among other things) and two flip-flops (with asynchronous set or reset capabilities)
• User I/O blocks: each user I/O pin is associated with an I/O block, which consists of an input buffer, an input flip-flop, a tri-state output buffer, and an output flip-flop
• Intra-FPGA tri-state buses, with tri-state buffers
• One crystal oscillator amplifier
• Two global clock buffers

Model	CLBs	User I/O (max)	Tri-state buses	Tri-state buffers per bus
XC3020, XC3020A, XC3020L, XC3120, XC3120A	64 (8×8)	64	16	9
XC3030, XC3030A, XC3030L, XC3130, XC3130A	100 (10×10)	80	20	11
XC3042, XC3042A, XC3042L, XC3142, XC3142A, XC3142L	144 (12×12)	96	24	13
XC3064, XC3064A, XC3064L, XC3164, XC3164A	224 (16×14)	120	32	15
XC3090, XC3090A, XC3090L, XC3190, XC3190A, XC3190L	320 (16×20)	144	40	17
XC3195, XC3195A	484 (22×22)	176	44	23

Note: the available user I/O amount varies with chip packaging.

XC4000, Spartan

The XC4000 and Spartan devices have the following user-programmable blocks: ^{[27] [28] [29] [30]}

• CLBs (Configurable Logic Blocks), each CLB containing:
  • two 4-input LUTs (F and G), which can be used as distributed RAM in 16×2 bit or 32×1 bit configurations (except on XC4000D devices)
  • a 3-input LUT (H) that can combine F and G outputs (for example, to implement a 5-input LUT)
  • two flip-flops (with clock enable and asynchronous set or reset)
  • carry chain logic
• User I/O blocks, one for each user I/O pin:
  • input buffer
  • tri-state output buffer
  • programmable pull-up or pull-down
  • input flip-flop (except on XC4000H devices)
  • output flip-flop (except on XC4000H devices)
  • optional delay element
  • fast capture latch (on some devices)
  • output multiplexer (on some devices)
• Edge decoders (essentially wide AND gates)
• Intra-FPGA tri-state buses, with tri-state buffers
• Global clock buffers
• Miscellaneous configuration logic (startup and readback control, boundary scan logic allowing custom user JTAG opcodes)

XC4000 family feature comparison

Family	Distributed RAM	H-LUT inputs	CLB flip-flop capabilities	IOB capabilities	Clock buffers
XC4000, XC4000A	asynchronous	1×F, 1×G, 1×general routing	Flip-flop	input and output flip-flops	4 primary + 4 secondary global buffers
XC4000H				no flip-flops
XC4000D	none			input and output flip-flops
XC4000E, XC4000L, Spartan	synchronous or asynchronous write, asynchronous read	3× any choice of F, G, general routing		input and output flip-flops with clock enable
XC4000EX, XC4000XL, XC4000XLA, XC4000XV			Flip-flop or latch	input and output flip-flops with clock enable, fast capture latch, output multiplexer	8 global buffers, 8 global low-skew buffers, 8 early clock buffers, 8 fast buffers
Spartan XL					8 global low-skew buffers

Model	Family	CLBs	User I/O (max)
XC4002A	XC4000A	64 (8×8)	64
XC4002XL	XC4000XL	64 (8×8)	64
XC4003	XC4000	100 (10×10)	80
XC4003A	XC4000A	100 (10×10)	80
XC4003H	XC4000H	100 (10×10)	160
XC4003E	XC4000E	100 (10×10)	80
XCS05	Spartan	100 (10×10)	77
XCS05XL	Spartan XL	100 (10×10)	77
XC4004A	XC4000A	144 (12×12)	96
XC4005	XC4000	196 (14×14)	112
XC4005A	XC4000A	196 (14×14)	112
XC4005H	XC4000H	196 (14×14)	192
XC4005E	XC4000E	196 (14×14)	112
XC4005L	XC4000L	196 (14×14)	112
XC4005XL	XC4000XL	196 (14×14)	112
XCS10	Spartan	196 (14×14)	112
XCS10XL	Spartan XL	196 (14×14)	112
XC4006	XC4000	256 (16×16)	128
XC4006E	XC4000E	256 (16×16)	128
XC4008	XC4000	324 (18×18)	144
XC4008E	XC4000E	324 (18×18)	144
XC4010	XC4000	400 (20×20)	160
XC4010D	XC4000D	400 (20×20)	160
XC4010E	XC4000E	400 (20×20)	160
XC4010L	XC4000L	400 (20×20)	160
XC4010XL	XC4000XL	400 (20×20)	160
XCS20	Spartan	400 (20×20)	160
XCS20XL	Spartan XL	400 (20×20)	160
XC4013	XC4000	576 (24×24)	192
XC4013D	XC4000D	576 (24×24)	192
XC4013E	XC4000E	576 (24×24)	192
XC4013L	XC4000L	576 (24×24)	192
XC4013XL	XC4000XL	576 (24×24)	192
XC4013XLA	XC4000XLA	576 (24×24)	192
XCS30	Spartan	576 (24×24)	192
XCS30XL	Spartan XL	576 (24×24)	192
XC4020E	XC4000E	784 (28×28)	224
XC4020XL	XC4000XL	784 (28×28)	224
XC4020XLA	XC4000XLA	784 (28×28)	224
XCS40	Spartan	784 (28×28)	205
XCS40XL	Spartan XL	784 (28×28)	205
XC4025E	XC4000E	1024 (32×32)	256
XC4028EX	XC4000EX	1024 (32×32)	256
XC4028XL	XC4000XL	1024 (32×32)	256
XC4028XLA	XC4000XLA	1024 (32×32)	256
XC4036EX	XC4000EX	1296 (36×36)	288
XC4036XL	XC4000XL	1296 (36×36)	288
XC4036XLA	XC4000XLA	1296 (36×36)	288
XC4044XL	XC4000XL	1600 (40×40)	320
XC4044XLA	XC4000XLA	1600 (40×40)	320
XC4052XL	XC4000XL	1936 (44×44)	352
XC4052XLA	XC4000XLA	1936 (44×44)	352
XC4062XL	XC4000XL	2304 (48×48)	384
XC4062XLA	XC4000XLA	2304 (48×48)	384
XC4085XL	XC4000XL	3136 (56×56)	448
XC4085XLA	XC4000XLA	3136 (56×56)	448
XC40110XV	XC4000XV	4096 (64×64)	448
XC40150XV	XC4000XV	5184 (72×72)	448
XC40200XV	XC4000XV	7056 (84×84)	448
XC40250XV	XC4000XV	8464 (92×92)	448

Note: the available user I/O amount varies with chip packaging.

XC5200

The XC5200 devices have the following user-programmable blocks: ^[31]

• CLBs (Configurable Logic Blocks): each CLB consists of 4 LCs (logic cells). Each logic cell consists of one 4-input LUT, a carry chain multiplexer, and one flip-flop (with clock enable and asynchronous reset). The CLB also has two dedicated multiplexers that can combine outputs of adjacent LCs (which can be used, among other purposes, to effectively combine the two 4-input LUTs into a 5-input LUT)
• User I/O blocks: each user I/O pin is associated with an I/O block, which consists of an input buffer and a tri-state output buffer
• Intra-FPGA tri-state buses, with tri-state buffers
• One crystal oscillator amplifier
• Four global clock buffers, one in each corner
• Miscellaneous configuration logic (startup and readback control, boundary scan logic allowing custom user JTAG opcodes)

Model	CLBs	User I/O (max)
XC5202, XC5202L	64 (10×10)	84
XC5204	120 (10×12)	124
XC5206, XC5206L	196 (14×14)	148
XC5210	324 (18×18)	196
XC5216, XC5216L	484 (22×22)	244

Note: the available user I/O amount varies with chip packaging.

XC6200

The XC6200 family is unusual in several ways: ^[32]

• as opposed to other early FPGAs where a design always takes up the whole device and is synthesized once, then usually stored in flash storage, XC6200 is dynamically reconfigurable in arbitrarily small chunks (down to a single logic cell), and is meant to be used along with an external CPU that can modify parts of design in real time
• the logic is not LUT based; instead, every logic cell consists of a 2-to-1 MUX whose inputs can be inverted or tied to constants (to implement arbitrary 2-input logic function) and a flip-flop
• the routing structure is fully documented, unusually simple, and hierarchical in nature, with the device made of 16×16 cell tiles and 4×4 cell blocks
• the configuration data format is likewise fully documented in the data sheet, ^[32] allowing (and encouraging) users to create logic designs without using vendor tools
• the part of configuration RAM that corresponds to unused area of circuit is explicitly allowed to be used for unrelated data storage

Model	Logic cells	IOBs	Configuration RAM (bits)	Notes
XC6209	2304 (48×48)	192	36K	listed as planned product, unclear if it ever reached production
XC6216	4096 (64×64)	256	65K
XC6236	9216 (96×96)	384	147K	listed as planned product, unclear if it ever reached production
XC6264	16384 (128×128)	512	262K	listed as planned product, unclear if it ever reached production

XC8100

The XC8100 family is unusual in several ways: ^[32]

• The configuration storage is made of one-time programmable antifuses, as opposed to other FPGAs (which use RAM cells and need to have configuration reuploaded upon power-up) and to CPLDs (which use non-volatile but multiple time programmable EPROM/EEPROM/flash storage).
• The logic is not LUT based; instead, the device is made of logic cells, which have 4 general inputs (+1 cascade input), 1 general output (+1 cascade output) and can be configured as either an AND gate or a sum-of-products, whose inputs can be inverted or tied to constants. This arrangement allows, as special cases, construction of a 2-input MUX or a D latch within a single cell, or combining two cells configured as D latches to construct a D flip-flop.

Model	Logic cells	User I/O (max)	Notes
XC8100	192 (24×8)	32
XC8101	384 (24×16)	72
XC8103	1024 (32×32)	128
XC8106	1728 (48×36)	168
XC8109	2688 (56×48)	192
XC8112	3744	248	planned product that never reached production
XC8116	4800	280	planned product that never reached production
XC8120	6144	320	planned product that never reached production

Virtex, Spartan-II

The Virtex and Spartan-II devices are made of the following user-programmable blocks:

• CLBs (configurable logic blocks), each made of two mostly-independent SLICEs, where a SLICE contains:
  • two 4-input LUTs, which can also be used as 16-bit distributed RAMs (which can be combined into 16×2 or 32×1 single-port or 16×1 dual port arrangements), or as 16-bit shift registers (which can be cascaded together to make longer shift registers)
  • carry chain logic consisting of two MUXCY+XORCY cell pairs, for construction of efficient ALUs or wide logic functions
  • two MULT_AND cells, to be combined with MUXCY+XORCY for construction of efficient multipliers
  • two hard multiplexer cells (MUXF5 and MUXF6) that can combine the LUT outputs together, allowing for efficient multiplexer tree construction or for construction of wider LUTs (5-input LUT out of two 4-input LUTs, or 6-input LUT out of four 4-input LUTs)
  • two flip-flops with clock enable and (configurable as synchronous or asynchronous) set and reset inputs; they can also be used as latches
• Intra-FPGA tri-state buses with tri-state buffers (two buffers per CLB)
• 4kbit true dual port block RAMs, which can be used in 4096×1, 2048×2, 1024×4, 512×8, or 256×16 configurations
• IOBs (I/O blocks), one per user I/O pin, containing:
  • several kinds of input buffer (selectable by user):
    • plain CMOS input buffer
    • differential input buffer using a VREF (voltage reference) pin for advanced I/O standards
    • (Virtex-E and Spartan-IIE only) differential input buffer using a pair of I/O pins for differential I/O standards (which has to be selected from a predefined list of pairs — each IOB has its associated other IOB that can be used to construct a differential pair)
  • tristate output buffer
  • configurable pull-up, pull-down, or keeper circuit
  • three flip-flops (for input, output, tristate enable), identical to the ones in CLBs
• the IOBs are grouped into 8 I/O banks (2 for each edge of the device), with each bank having a separate power supply, allowing for usage of several I/O standards with conflicting voltage requirements in a single device
• DLLs (delay-locked loops) that can be used to phase-align, deskew, and phase-shift incoming clock signals
• 4 global clock buffers
• miscellaneous configuration logic (startup control, readback data capture, JTAG control)

The Virtex and Spartan-II devices are functionally identical to each other and differ only in available size range, performance, and packaging options. The Spartan-IIE devices use the same die as the corresponding Virtex E devices, but have some block RAM and DLLs disabled.

Model	Family	CLBs	4-LUTs (CLBs×4)	Block RAMs (4kbit each)	User I/O (max)	User I/O differential pairs (max)	DLLs
XC2S15	Spartan-II [33]	96 (12×8)	384	4	86	-	4
XC2S30	Spartan-II	216 (18×12)	864	6	92	-	4
XCV50	Virtex [34]	384 (24×16)	1536	8	180	-	4
XC2S50	Spartan-II	384 (24×16)	1536	8	176	-	4
XCV50E	Virtex E [35]	384 (24×16)	1536	16	176	83	8
XC2S50E	Spartan-IIE [36]	384 (24×16)	1536	8	182	83	4
XCV100	Virtex	600 (30×20)	2400	10	180	-	4
XC2S100	Spartan-II	600 (30×20)	2400	10	176	-	4
XCV100E	Virtex E	600 (30×20)	2400	20	196	83	8
XC2S100E	Spartan-IIE	600 (30×20)	2400	10	202	86	4
XCV150	Virtex	864 (36×24)	3456	12	260	-	4
XC2S150	Spartan-II	864 (36×24)	3456	12	260	-	4
XC2S150E	Spartan-IIE	864 (36×24)	3456	12	265	114	4
XCV200	Virtex	1176 (42×28)	4704	14	284	-	4
XC2S200	Spartan-II	1176 (42×28)	4704	14	284	-	4
XCV200E	Virtex E	1176 (42×28)	4704	28	284	119	8
XC2S200E	Spartan-IIE	1176 (42×28)	4704	14	289	120	4
XCV300	Virtex	1536 (48×32)	6144	16	316	-	4
XCV300E	Virtex E	1536 (48×32)	6144	32	316	137	8
XC2S300E	Spartan-IIE	1536 (48×32)	6144	16	329	120	4
XCV400	Virtex	2400 (60×40)	9600	20	404	-	4
XCV400E	Virtex E	2400 (60×40)	9600	40	404	183	8
XC2S400E	Spartan-IIE	2400 (60×40)	9600	40	410	172	4
XCV405E	Virtex EM [37]	2400 (60×40)	9600	140	404	183	8
XCV600	Virtex	3456 (72×48)	13824	24	512	-	4
XCV600E	Virtex E	3456 (72×48)	13824	72	512	247	8
XC2S600E	Spartan-IIE	3456 (72×48)	13824	72	514	205	4
XCV800	Virtex	4704 (84×56)	18816	28	512	-	4
XCV812E	Virtex EM	4704 (84×56)	18816	280	556	201	8
XCV1000	Virtex	6144 (96×64)	24576	32	512	-	4
XCV1000E	Virtex E	6144 (96×64)	24576	96	660	281	8
XCV1600E	Virtex E	7776 (108×72)	31104	144	724	344	8
XCV2000E	Virtex E	9600 (120×80)	38400	160	804	344	8
XCV2600E	Virtex E	12696 (138×92)	50784	184	804	344	8
XCV3000E	Virtex E	16224 (156×104)	64896	208	804	344	8

Note: the available user I/O amount varies with chip packaging. Additionally, not all I/Os can be used as part of a differential pair, so the available differential pair count can be smaller than half of the available I/O count.

Virtex-II

The Virtex-II devices are made of the following user-programmable blocks:

• CLBs (configurable logic blocks), which contain 4 logic SLICEs, which are an improved version of the Virtex SLICE, with the following differences:
  • when used as distributed RAM, the LUTs of multiple SLICEs within a CLB can be combined to obtain the following RAM configurations:
    • 16×1 single port (half SLICE)
    • 16×2 single port (one SLICE)
    • 32×1 single port (one SLICE)
    • 64×1 single port (two SLICEs)
    • 128×1 single port (four SLICEs)
    • 16×1 dual port (two half-SLICEs — utilizes one LUT of two different SLICEs each)
    • 16×2 dual port (two SLICEs)
    • 32×1 dual port (two SLICEs)
    • 64×1 dual port (four SLICEs)
  • the wide function multiplexers can now be used in a 4-level tree (as opposed to a 2-level tree on Virtex), allowing for construction of up to 8-input LUTs (out of 16 4-input LUTs from two neighbouring CLBs)
  • the carry chain has been enhanced with the addition of an ORCY cell allowing for efficient sum-of-products mapping
• 18kbit true dual port block RAMs, which can be used in 16386×1, 8192×2, 4096×4, 2048×9, 1024×18, 512×36 configurations (with the narrow configurations having only 16kbit available, since they cannot access the parity bits)
• hard multiplier blocks (two signed 18-bit inputs, 36-bit output) — always exactly one per block RAM, since they reside in a shared tile
• IOBs (I/O blocks), one per user I/O pin, which are an improved version of the Virtex IOB with the following differences:
  • the three I/O flip-flops are replaced with pairs of flip-flops for DDR (double data rate) capability
  • new DCI (Digitally Controlled Impedance) functionality — the device has a per-bank circuit that can utilize an external precision resistor pair connected to user I/O pins to calibrate I/O resistance on remaining user pins, providing very good impedance matching
  • support for multiple new I/O standards, including native differential I/O
• DCMs (digital clock managers), which replace Virtex DLLs, adding frequency synthesis and clock divider capability
• 16 global clock buffers
• Miscellaneous configuration logic (startup control, readback data capture, JTAG control, and the ICAP — Internal Configuration Access Port). The ICAP can be used to dynamically reprogram parts of the FPGA after the initial configuration from within the FPGA itself.

Virtex-II Pro devices include some additional blocks:

• RocketIO transceivers: high-speed parallel-to-serial transmitters and serial-to-parallel receivers with clock data recovery and 8b/10b encoders/decoders. They have a speed range of 600 Mb/s to 3.125 Gb/s and parallel width of 8, 16, or 32 bits (or 10, 20, 40 bits in 8b10b bypass mode)
• RocketIO X transceivers: improved transceivers with 64b/66b encoding/decoding (in addition to 8b/10b), speed range of 2.488 Gb/s to 6.25 Gb/s (XC2VPX20) or fixed speed of 4.25 Gb/s (XC2VPX70), and parallel width of 8, 16, 32, or 64 bits (or 10, 20, 40, 80 bits in 8b/10b bypass mode)
• Embedded PPC405 cores

Model	Family	CLBs	4-LUTs (CLBs×8)	Multiplier blocks and block RAMs (18kbit each)	DCMs	User I/O (max)	Multi-gigabit transceivers (max)	PPC cores
XC2V40	Virtex-II [38]	64 (8×8)	512	4	4	88	-	-
XC2V80	Virtex-II	128 (8×16)	1024	8	4	120	-	-
XC2V250	Virtex-II	384 (16×24)	3072	24	8	200	-	-
XC2V500	Virtex-II	768 (24×32)	6144	32	8	264	-	-
XC2V1000	Virtex-II	1280 (32×40)	10240	40	8	432	-	-
XC2V1500	Virtex-II	1920 (40×48)	15360	48	8	528	-	-
XC2V2000	Virtex-II	2688 (48×56)	21504	56	8	624	-	-
XC2V3000	Virtex-II	3584 (56×64)	28672	96	12	720	-	-
XC2V4000	Virtex-II	5760 (72×80)	46080	120	12	912	-	-
XC2V6000	Virtex-II	8448 (88×96)	67584	144	12	1104	-	-
XC2V8000	Virtex-II	11648 (104×112)	93184	168	12	1108	-	-
XC2VP2	Virtex-II Pro [39]	352	2816	12	4	204	RocketIO ×4	-
XC2VP4	Virtex-II Pro	752	6016	28	4	348	RocketIO ×4	1
XC2VP7	Virtex-II Pro	1232	9856	44	4	396	RocketIO ×8	1
XC2VP20	Virtex-II Pro	2320	18560	88	8	564	RocketIO ×8	2
XC2VPX20	Virtex-II Pro X	2448	19584	88	8	552	RocketIO X ×8	1
XC2VP30	Virtex-II Pro	3424	27392	136	8	644	RocketIO ×8	2
XC2VP40	Virtex-II Pro	4848	38784	192	8	804	RocketIO ×12	2
XC2VP50	Virtex-II Pro	5904	47232	232	8	852	RocketIO ×16	2
XC2VP70	Virtex-II Pro	8272	66176	328	8	996	RocketIO ×20	2
XC2VPX70	Virtex-II Pro X	8272	66176	308	8	992	RocketIO X ×20	2
XC2VP100	Virtex-II Pro	11024	88192	444	12	1164	RocketIO ×20	2

Note: the available user I/O and multi-gigabit transceiver amount varies with chip packaging.

Note: the CLB count for Virtex-II Pro devices is no longer a simple columns×rows multiplication, as the CLB grid contains holes for the PowerPC cores.

Spartan-3

The Spartan-3 devices are made of:

• CLBs (configurable logic blocks), which are very similar to Virtex-II, with some modifications:
  • Only two of the four SLICEs in the CLB can now be used as distributed RAM or shift registers. The SLICEs that can be used as distributed RAM or shift registers are called SLICEMs, and the remaining SLICEs are called SLICELs.
  • The available distributed RAM configurations are now:
    • 16×1 single port (half SLICEM)
    • 16×2 single port (one SLICEM)
    • 32×1 single port (one SLICEM)
    • 64×1 single port (two SLICEMs)
    • 16×1 double port (one SLICEM)
    • 32×1 double port (two SLICEMs)
  • The ORCY cell has been removed
• 18kbit true dual port block RAMs, with the following variants:
  • Spartan-3, Spartan-3E: identical to Virtex-II
  • Spartan-3A, Spartan-3AN: adds per-byte write enable signals
  • Spartan-3A DSP: like Spartan-3A, plus adds optional output pipeline registers (for faster clock-to-out time)
• hard multiplier blocks or DSP cells:
  • Spartan-3: MULT18X18, identical to Virtex-II
  • Spartan-3E, Spartan-3A, Spartan-3AN: MULT18X18SIO, adds extra input registers for faster pipelined operation
  • Spartan-3A DSP: DSP48A, a complete DSP ALU consisting of an 18×18 multiplier plus 48-bit accumulator
• IOBs (I/O blocks), one per user pin:
  • Spartan-3: similar to Virtex-II, arranged in 8 banks
  • Spartan-3E: simplified version, removes DCI capability, arranged in 4 banks (one for each device edge)
  • Spartan-3A, Spartan-3AN, Spartan-3A DSP: like Spartan-3E, but with support for newer I/O standards, and with somewhat differing capabilities of top/bottom banks and left/right banks
• DCMs, similar to Virtex-II
• 8 (Spartan-3) or 24 (Spartan-3E, 3A, 3AN, 3A DSP) global clock buffers
• Miscellaneous configuration logic (like Virtex-II, but with disabled ICAP access)
• Spartan-3A, 3AN, 3A DSP only: access to a unique device serial number (so-called device DNA)
• Spartan-3AN only: access port to the in-package SPI flash

Model	Family	CLBs	4-LUTs (CLBs×8)	Block RAMs (18kbit each)	Multiplier blocks	DCMs	User I/O (max)	Differential I/O pairs (max)
XC3S50	Spartan-3 [40]	192 (12×16)	1536	4	4	2	124	56
XC3S200	Spartan-3	480 (20×24)	3840	12	12	4	173	76
XC3S400	Spartan-3	896 (28×32)	7168	16	16	4	264	116
XC3S1000, XC3S1000L	Spartan-3	1920 (40×48)	15360	24	24	4	391	175
XC3S1500, XC3S1500L	Spartan-3	3328 (52×64)	26624	32	32	4	487	221
XC3S2000	Spartan-3	5120 (64×80)	40960	40	40	4	565	270
XC3S4000	Spartan-3	6912 (72×96)	55296	96	96	4	633	300
XC3S5000	Spartan-3	8320 (80×104)	66560	104	104	4	633	300
XC3S100E	Spartan-3E [41]	240	1920	4	4	2	108	40
XC3S250E	Spartan-3E	612	4896	12	12	4	172	68
XC3S500E	Spartan-3E	1164	9312	20	20	4	232	92
XC3S1200E	Spartan-3E	2168	17344	28	28	8	304	124
XC3S1600E	Spartan-3E	3688	29504	36	36	8	376	156
XC3S50A, XC3S50AN	Spartan-3A/3AN [42]	176	1408	3	3	2	144	64
XC3S200A, XC3S200AN	Spartan-3A/3AN	448	3584	16	16	4	248	112
XC3S400A, XC3S400AN	Spartan-3A/3AN	896	7168	20	20	4	311	142
XC3S700A, XC3S700AN	Spartan-3A/3AN	1472	11776	20	20	8	372	165
XC3S1400A, XC3S1400AN	Spartan-3A/3AN	2816	22528	32	32	8	502	227
XC3SD1800A	Spartan-3A DSP [43]	4160	33280	84	DSP48A ×84	8	519	227
XC3SD3400A	Spartan-3A DSP	5968	47744	126	DSP48A ×126	8	469	213

Note: the available user I/O amount varies with chip packaging. Additionally, not all I/Os can be used as part of a differential pair, so the available differential pair count can be smaller than half of the available I/O count.

Note: for families other than Spartan-3, the CLB grid is irregular and includes holes for block RAMs and DCMs, so the CLB count is not a simple multiplication of columns×rows

Virtex-4

The Virtex-4 devices are made of: ^{[44] [45]}

• CLBs (configurable logic blocks), almost unchanged from Spartan-3
• 18kbit true dual port block RAMs, very similar to Spartan-3A DSP, but with some new capabilities:
  • two adjacent block RAMs can be combined to make a 32768×1 RAM
  • each block RAM can be used in FIFO mode (in 4096×4, 2048×9, 1024×18, 512×36 configurations) where address inputs are replaced with hardware FIFO counter functionality
• DSP48 blocks, ^[46] ALU blocks with 18×18 multiplier and 48-bit accumulator
• IOBs (I/O blocks, one per user pin): in addition to Virtex-II capabilities, they support ISERDES and OSERDES blocks which do simple serial-to-parallel and parallel-to-serial conversion (2, 3, 4, 5, 6, 7, or 8 bit wide in SDR mode; 4, 6, 8, or 10 bit wide in DDR mode)
• IOBs are arranged into I/O banks; in a change from earlier FPGAs with fixed bank number, number of I/O banks on Virtex-4 varies with device size, but banks now have a more uniform size of 16 or 32 I/O pins, with the exception of special bank 0 that contains dedicated configuration pins. Each bank has two or four I/O clock buffers for fast clocks used by the SERDES blocks.
• DCMs, similar to Virtex-II/Spartan-3
• PMCDs (phase-matched clock dividers), an unusual clock divider block
• 32 global clock buffers
• Multiple clock regions, with 2 regional clock buffers per region
• Miscellaneous configuration logic: like Virtex-II, plus:
  • configuration data ECC checking circuitry
  • 32-bit user data access port

The Virtex-4 FX devices additionally contain:

• RocketIO multi-gigabit transceivers with a speed range of 622 Mb/s to 6.5 Gb/s and parallel width of 8, 16, 32, or 64 bits (10, 20, 40, or 80 bits in 8b/10b bypass mode)
• Embedded PPC405 cores
• Embedded gigabit ethernet MAC blocks (two per PPC core)

Model	Sub-family	CLBs	4-LUTs (CLBs×8)	Block RAMs (18kbit each)	DSP48 blocks	DCMs	PMCDs	Clock Regions	I/O banks	User I/Os (max)	Gigabit transceivers (max)	PPC cores
XC4VLX15	LX	1536 (24×64)	12288	48	32	4	-	8	9	320	-	-
XC4VLX25	LX	2688 (28×96)	21504	72	48	8	4	12	11	448	-	-
XC4VLX40	LX	4608 (36×128)	36864	96	64	8	4	16	13	640	-	-
XC4VLX60	LX	6656 (52×128)	53248	160	64	8	4	16	13	640	-	-
XC4VLX80	LX	8960 (56×160)	71680	200	80	12	8	20	15	768	-	-
XC4VLX100	LX	12288 (64×192)	98304	240	96	12	8	24	17	960	-	-
XC4VLX160	LX	16896 (88×192)	135168	288	96	12	8	24	17	960	-	-
XC4VLX200	LX	22272 (116×192)	178176	336	96	12	8	24	17	960	-	-
XC4VSX25	SX	2560 (40×64)	20480	128	128	4	-	8	9	420	-	-
XC4VSX35	SX	3840 (40×96)	30720	192	192	8	4	12	11	448	-	-
XC4VSX55	SX	6144 (48×128)	49152	320	512	8	4	16	13	640	-	-
XC4VFX12	FX	1368	10944	36	32	4	-	8	9	320	-	1
XC4VFX20	FX	2136	17088	68	32	4	-	8	9	320	8	1
XC4VFX40	FX	4656	37248	144	48	8	4	12	11	448	12	2
XC4VFX60	FX	6320	50560	232	128	12	8	16	13	576	16	2
XC4VFX100	FX	10544	84352	376	160	12	8	20	15	768	20	2
XC4VFX140	FX	15792	126336	552	192	20	8	24	17	896	24	2

Note: the I/O banks count includes special bank 0, which contains only dedicated configuration I/O (no user I/O)

Note: the available user I/O, I/O bank, and multi-gigabit transceiver amount varies with chip packaging.

Note: the CLB count for FX devices is no longer a simple columns×rows multiplication, as the CLB grid contains holes for the PowerPC cores.

Virtex-5

The Virtex-5 devices are made of: ^{[47] [48]}

• CLBs (configurable logic blocks) with a new, 6-input-LUT based construction:
  • every CLB is made of two SLICEs — either two SLICELs or one SLICEL and one SLICEMs; the exact proportion of SLICEMs in a device varies, but at least 50% of CLBs contain a SLICEM (with a higher proportion on DSP-heavy devices)
  • every SLICE contains four 6-input LUTs, each of which can be used as:
    • a 6-input LUT
    • two 5-input LUTs with shared inputs (ie. the LUT is fracturable)
    • (SLICEM only) 32×2 or 64×1 distributed RAM, which can be combined with other distributed RAMs within the same SLICEM
    • (SLICEM only) 16-bit or 32-bit shift register, which can be combined with other shift registers within the same SLICEM, for maximum of 128-bit shift register in a single SLICEM
  • the arrangement of distributed RAMs within the SLICEM is quite complex and only some configurations can be obtained; the SLICEM usage combinations allowed by vendor tools are:
    • 32×8, 64×4, 128×2, or 256×1 single port RAM
    • 32×4, 62×2, 128×1 dual port RAM
    • 32×2, 64×1 quad port RAM
    • 32×6, 64×3 simple dual port RAM
  • every SLICE contains four flip-flops with clock enable and (configurable as synchronous or asynchronous) set and reset inputs; they can also be used as latches
  • every SLICE contains a carry chain, identical in functionality to the one used since Virtex (made of MUXCY and XORCY cells), but now represented as a single CARRY4 cell for the whole SLICE (mostly for more accurate timing simulation)
  • compared to Virtex-4 SLICEs, the MULT_AND cell is gone; however, its functionality can be trivially replicated by using one half of the corresponding now-fracturable LUT
  • every SLICE contains a two-level tree of wide LUT multiplexers that can be used to combine the outputs of the LUTs, and can eg. combine the four LUTs within a SLICE into a single 8-input LUT
• 36kbit splittable true dual port block RAMs, with some new capabilities compared to Virtex-4:
  • the base block RAM is twice the size of Virtex-4; however, any given block RAM can be split into two 18kbit halves functioning independently (but only one half can use the hardware FIFO mode)
  • the available true dual port configurations of the full (36kbit) block RAM are: 32768×1, 16384×2, 8192×4, 4096×9, 2048×18, 1024×36, plus a special 65536×1 mode obtained by combining two adjacent RAMs
  • the available true dual port configurations of the half (18kbit) block RAM are: 16384×1, 8192×2, 4096×4, 2048×9, 1024×18
  • in addition to true dual port mode, the block RAMs can also be used in simple dual port mode, which doubles the maximum width of the block RAM, allowing for 512×72 (full block RAM) and 512×36 (half block RAM) configurations
  • a hardware 64-bit SECDED ECC encoder/decoder has been added, which can be used with the simple dual port mode of the full block RAM to obtain a 512×64 block RAM with error correction and detection
• DSP48E blocks, ^[49] improved version of Virtex-4 DSP48 blocks with 25×18 multiplier, 48-bit accumulator (with new bitwise operations function), and pattern detector
• IOBs (I/O blocks, one per user pin): with minor improvements from Virtex-4 (mainly new I/O standard support)
• The I/O bank arrangement is similar to Virtex-4, but the banks have size of 20 or 40 user I/O pins
• CMTs (clock management tiles), each of which has:
  • two DCMs (similar to Virtex-4 DCM)
  • one PLL, which has similar general functionality as the old DCM, but is made of analog circuitry and has different set of available outputs
• the Virtex-4 PMCDs are gone; some of their functionality can be replicated by using PLLs instead
• 32 global clock buffers
• multiple clock regions, with two regional clock buffers per region
• a single system monitor: an analog-to-digital converter used for monitoring FPGA supply voltages, temperature, and possibly other, external analog signals
• Miscellaneous configuration logic: like Virtex-4, plus:
  • unique device serial number access (identical to the DNA port in Spartan-3A)
  • read-only access to user-programmable efuses
• (LXT and SXT devices) GTP ^[50] multi-gigabit transceivers with a speed range of 100 Mb/s to 3.75 Gb/s and parallel width of 8, or 16 bits (10 or 20 bits in 8b/10b bypass mode)
• (FXT and TXT devices) GTX ^[51] multi-gigabit transceivers with a speed range of 150 Mb/s to 6.5 Gb/s and parallel width of 8, 16, or 32 bits (10, 20, or 40 bits in 8b/10b bypass mode)
• (FXT devices) embedded PPC440 cores
• (LXT, SXT, FXT, TXT devices) embedded gigabit Ethernet MAC cores
• (LXT, SXT, FXT, TXT devices) embedded PCI Express cores capable of Gen1.1 ×8 operation

Model	Sub-family	CLBs	6-LUTs (=CLBs×8)	SLICEMs	Block RAMs (36kbit each)	DSP48E blocks	DCMs	PLLs	Clock regions	I/O banks (max)	User I/Os (max)	Gigabit transceivers (max)	PPC cores	Ethernet MACs	PCI Express cores
XC5VLX20T	LXT	1560 (26×60)	12480	840	26	24	2	1	6	7	172	4 GTP	-	2	1
XC5VLX30	LX	2400 (30×80)	19200	1280	32	32	4	2	8	13	400	-	-	-	-
XC5VLX30T	LXT	2400 (30×80)	19200	1280	36	32	4	2	8	12	360	8 GTP	-	4	1
XC5VLX50	LX	3600 (30×120)	28800	1920	48	48	12	6	12	17	560	-	-	-	-
XC5VLX50T	LXT	3600 (30×120)	28800	1920	60	48	12	6	12	15	480	12 GTP	-	4	1
XC5VLX85	LX	6480 (54×120)	51840	3360	96	48	12	6	12	17	560	-	-	-	-
XC5VLX85T	LXT	6480 (54×120)	51840	3360	108	48	12	6	12	15	480	12 GTP	-	4	1
XC5VLX110	LX	8640 (64×160)	69120	4480	128	64	12	6	16	23	800	-	-	-	-
XC5VLX110T	LXT	8640 (64×160)	69120	4480	148	64	12	6	16	20	680	16 GTP	-	4	1
XC5VLX155	LX	12160 (76×160)	97280	6560	192	128	12	6	16	23	800	-	-	-	-
XC5VLX155T	LXT	12160 (76×160)	97280	6560	212	128	12	6	16	20	680	16 GTP	-	4	1
XC5VLX220	LX	17280 (108×160)	138240	9120	192	128	12	6	16	23	800	-	-	-	-
XC5VLX220T	LXT	17280 (108×160)	138240	9120	212	128	12	6	16	20	680	16 GTP	-	4	1
XC5VLX330	LX	25920 (108×240)	207360	13680	288	192	12	6	24	33	1200	-	-	-	-
XC5VLX330T	LXT	25920 (108×240)	207360	13680	324	192	12	6	24	27	960	20 GTP	-	4	1
XC5VSX35T	SXT	2720 (34×80)	21760	2080	84	192	4	2	8	12	360	8 GTP	-	4	1
XC5VSX50T	SXT	4080 (34×120)	32640	3120	132	288	12	6	12	15	480	12 GTP	-	4	1
XC5VSX95T	SXT	7360 (46×160)	58880	6080	244	640	12	6	16	19	640	16 GTP	-	4	1
XC5VSX240T	SXT	18720 (78×240)	149760	16800	516	1056	12	6	24	27	960	24 GTP	-	4	1
XC5VTX150T	TXT	11600 (58×200)	92800	6000	228	80	12	6	20	20	680	40 GTX	-	4	1
XC5VTX240T	TXT	18720 (78×240)	149760	9600	324	96	12	6	24	20	680	48 GTX	-	4	1
XC5VFX30T	FXT	2560	20480	1520	68	64	4	2	8	12	360	8 GTX	1	4	1
XC5VFX70T	FXT	5600	44800	3280	148	128	12	6	16	19	640	16 GTX	1	4	3
XC5VFX100T	FXT	8000	64000	4960	228	256	12	6	16	20	680	16 GTX	2	4	3
XC5VFX130T	FXT	10240	81920	6320	298	320	12	6	20	24	840	20 GTX	2	6	3
XC5VFX200T	FXT	15360	122880	9120	456	384	12	6	24	27	960	24 GTX	2	8	4

Note: the I/O banks count includes special bank 0, which contains only dedicated configuration I/O (no user I/O)

Note: the available user I/O, I/O bank, and multi-gigabit transceiver amount varies with chip packaging.

Note: the CLB count for FXT devices is no longer a simple columns×rows multiplication, as the CLB grid contains holes for the PowerPC cores.

Virtex-6

The Virtex-6 devices are made of: ^[52]

• CLBs (configurable logic blocks): ^[53] like the Virtex-5 CLBs, with some minor modifications:
  • every SLICE now contains 8 flip-flops (two for each 6-LUT) instead of 4
  • the flip-flops now have only one set/reset input (ie. it is impossible to have a flip-flop with both a set and a reset input)
• 36 Kibit splittable true dual port block RAM: ^[54] a slightly improved version of the Virtex-5 block RAM
• DSP48E1 blocks, ^[55] upgraded version of Virtex-5 DSP48E, adding a pre-adder block
• IOBs (I/O blocks, one per user pin): ^[56] with minor improvements from Virtex-5 (mainly new I/O standard support), and with notable removal of 3.3 V I/O support (max supported I/O voltage is 2.5V)
• The I/O bank arrangement is similar to Virtex-5, but the banks have constant size of 40 user I/O pins
• CMTs (clock management tiles), ^[57] each of which contains two MMCMs (mixed-mode clocking managers), which are analog-based replacements for the old DCMs, and are an evolution of the Virtex-5 PLLs
• 32 global clock buffers
• multiple clock regions, with two or four regional clock buffers per region
• a single system monitor, like Virtex-5
• Miscellaneous configuration logic: like Virtex-5
• (non-LX devices) GTX multi-gigabit transceivers with a speed range of 480 Mb/s to 6.6 Gb/s and parallel width of 8, 16, or 32 bits (10, 20, or 40 bits in 8b/10b bypass mode)
• (some HXT devices) GTH multi-gigabit transceivers with a speed range of 2.488 Gb/s to 11.2 Gb/s and parallel width of 8, 16, 32, or 64 bits (10, 20, 40, or 80 bits in 8b/10b bypass mode)
• (non-LX devices) embedded gigabit Ethernet MAC cores
• (non-LX devices) embedded PCI Express cores capable of Gen2 ×8 operation

Model	Sub-family	CLBs	6-LUTs (=CLBs×8)	SLICEMs	36 Kibit block RAMs	DSP48E1 blocks	MMCMs	Clock Regions	I/O banks (max)	User I/Os (max)	Gigabit transceivers (max)	Ethernet MACs	PCI Express Cores
XC6VLX75T	LXT	5820	46560	4180	156	288	6	6	9	360	12 GTX	4	1
XC6VCX75T	CXT [58]	5820	46560	4180	156	288	6	6	9	360	12 GTX	1	1
XC6VLX130T	LXT	10000	80000	6960	264	480	10	10	15	600	20 GTX	4	2
XC6VCX130T	CXT	10000	80000	6960	264	480	10	10	15	600	16 GTX	1	2
XC6VLX195T	LXT	15600	124800	12160	344	640	10	10	15	600	20 GTX	4	2
XC6VCX195T	CXT	15600	124800	12160	344	640	10	10	15	600	16 GTX	1	2
XC6VLX240T	LXT	18840	150720	14600	416	768	12	12	18	720	24 GTX	4	2
XC6VCX240T	CXT	18840	150720	14600	416	768	12	12	18	600	16 GTX	1	2
XC6VLX365T	LXT	28440	227520	16520	416	576	12	12	18	720	24 GTX	4	2
XC6VLX550T	LXT	42960	343680	24800	632	864	18	18	30	1200	36 GTX	4	2
XC6VLX760	LX	59280	474240	33120	720	864	18	18	30	1200	-	-	-
XC6VSX315T	SXT	24600	196800	20360	704	1344	12	12	18	720	24 GTX	4	2
XC6VSX475T	SXT	37200	297600	30560	1064	2016	18	18	21	840	36 GTX	4	2
XC6VHX250T	HXT	19680	157440	12160	504	576	12	12	8	320	48 GTX	4	4
XC6VHX255T	HXT	19800	158400	12200	516	576	12	12	12	480	24 GTX + 24 GTH	2	2
XC6VHX380T	HXT	29880	239040	18280	768	864	18	18	18	720	48 GTX + 24 GTH	4	4
XC6VHX565T	HXT	44280	354240	25480	912	864	18	18	18	720	24 GTX + 24 GTH	4	4

Note: the I/O banks count does not include special bank 0, which contains only dedicated configuration I/O (no user I/O)

Note: the available user I/O, I/O bank, and multi-gigabit transceiver amount varies with chip packaging.

Note: Virtex-6 CLB grid is irregular and contains holes (for configuration center and PCI Express blocks), and so the CLB count is no longer a simple columns×rows multiplication

Note: The CXT devices use an identical die to the corresponding LXT devices, but with some disabled blocks and reduced performance (GTX transceivers have a speed range of 150 Mb/s to 3.75 Gb/s).

Spartan-6

The Spartan-6 devices are basically Spartan-3A DSP devices upgraded with some Virtex-6 technology. They are made of: ^[59]

• CLBs (configurable logic blocks), ^[60] similar to Virtex-6, but with some changes:
  • SLICEs now come in three types: SLICEX, SLICEL, SLICEM; SLICEX is a bare-bones version of SLICEL (wide LUT multiplexers and carry chain have been removed, only LUTs and flip-flops remain)
  • every CLB contains two SLICEs: either one SLICEX + one SLICEL, or one SLICEX + one SLICEM; around 50% of the CLBs contain a SLICEM
• 18kbit true dual port block RAMs, ^[61] similar to Spartan-3A DSP, but with additional capabilities:
  • the full 18kbit block RAM can be split into two 9kbit halves, with available configurations of 8192×1, 4096×2, 2048×4, 1024×9, 512×18
  • in split mode, the half block RAMs additionally support a simple dual port mode in 256×36 configuration
• DSP48A1 blocks, ^[62] which are an upgraded version of the DSP48A blocks of Spartan-3A DSP devices
• IOBs (I/O blocks, one per user pin): ^[63]
  • the electrical capabilities are similar to Spartan-3A (though with new I/O standards supported); there is no DCI support, but user can select an uncalibrated I/O impedance from several settings
  • Virtex-6-like ISERDES and OSERDES blocks are present (though with fewer capabilities than Virtex-6 devices), with associated fast I/O block buffers
  • the I/O bank arrangement is similar to Spartan-3A devices, but with a minor change: small devices have 4 banks (one for each device edge), while large devices have 6 banks (with the left and right edges split into two banks
• MCBs (memory controller blocks), ^[64] hard memory controllers supporting DDR, DDR2, DDR3, and LPDDR memory
• CMTs (clock management tiles), ^[65] each of which has:
  • two DCMs, similar to Spartan-3A DCMs, but with new clock generator mode and dynamic reconfiguration capabilities
  • one PLL, similar to Virtex-5 PLLs
• 16 global clock buffers
• multiple clock regions, with 16 regional clock buffers each, which can replace the corresponding global clock buffer output for that region
• Miscellaneous configuration logic: like Spartan-3A, plus circuitry performing live configuration memory scanning with CRC error detection (but no correction)
• (SXT devices only) GTP multi-gigabit transceivers ^[66] with speed ranges of 614 Mb/s to 810 Mb/s, 1.22 Gb/s to 1.62 Gb/s, and 2.45 Gb/s to 3.125 Gb/s, 8b/10b encoder and decoder, and parallel width of 8, 16, or 32 bits (10, 20, or 40 bits in 8b/10b bypass mode)
• (SXT devices only) embedded PCI Express cores capable of Gen1.1 ×1 operation

Model	Sub-family	CLBs	6-LUTs (=CLBs×8)	SLICEMs	Block RAMs (18kbit each)	DSP48A1 blocks	DCMs	PLLs	Clock Regions	I/O banks	User I/Os (max)	MCBs	Gigabit transceivers (max)	PCI Express Cores	Notes
XC6SLX4	LX	300	2400	300	12	8	4	2	4	4	132	-	-	-	uses the same die as XC6SLX9, with lots of disabled blocks
XC6SLX9	LX	715	5720	360	32	16	4	2	4	4	200	2	-	-
XC6SLX16	LX	1139	9112	544	32	32	4	2	4	4	232	2	-	-
XC6SLX25	LX	1879	15032	916	52	38	4	2	5	4	266	2	-	-	uses the same die as XC6SLX25T, with disabled transceivers
XC6SLX25T	LXT	1879	15032	916	52	38	4	2	5	4	250	2	2	1
XC6SLX45	LX	3411	27288	1602	116	58	8	4	8	4	358	2	-	-	uses the same die as XC6SLX45T, with disabled transceivers
XC6SLX45T	LXT	3411	27288	1602	116	58	8	4	8	4	296	2	4	1
XC6SLX75	LX	5831	46648	2768	172	132	12	6	12	6	408	4	-	-	uses the same die as XC6SLX75T, with disabled transceivers
XC6SLX75T	LXT	5831	46648	2768	172	132	12	6	12	6	348	4	8	1
XC6SLX100	LX	7911	63288	3904	268	180	12	6	12	6	480	4	-	-	uses the same die as XC6SLX100T, with disabled transceivers
XC6SLX100T	LXT	7911	63288	3904	268	180	12	6	12	6	498	4	8	1
XC6SLX150	LX	11519	92152	5420	268	180	12	6	12	6	576	4	-	-	uses the same die as XC6SLX150T, with disabled transceivers
XC6SLX150T	LXT	11519	92152	5420	268	180	12	6	12	6	540	4	8	1

7 Series

The 7 series devices are made of: ^[67]

• CLBs (configurable logic blocks), functionally identical to Virtex-6
• 36kbit splittable true dual port block RAM, functionally identical to Virtex-6
• DSP48E1 blocks, functionally identical to Virtex-6
• IOBs (I/O blocks, one per user pin): ^[68] derived from Virtex-6, but with multiple changes:
  • the IOBs now come in two kinds
    • HR (high range) I/O, which once again supports I/O voltage up to 3.3V, but has no DCI support
    • HP (high performance) I/O, which supports I/O voltage up to 1.8V, with DCI support
  • the I/O banks now have 50 I/O pins each, as follows:
    • 24 differential I/O pairs, split into 4 "byte groups" of 6 I/O pairs (or 12 I/O pins)
    • 2 single I/O pins without differential pair
  • the CMTs (clock management tiles) ^[69] are now tightly coupled with I/O banks: there is one CMT for every I/O bank, and it contains:
    • one MMCM, similar to Virtex-6 MMCM
    • one PLL, which is a version of MMCM with less advanced functionality
    • four input and four output asynchronous FIFOs, designed for memory controller usage, but available for any application
    • undocumented phaser circuitry used only by the Xilinx memory controller IPs
• global clock buffers (usually 32 of them, but some devices have only 16, and 3D devices have 32 for every die)
• multiple clock regions, with 4 regional clock buffers per region
• (not on the smallest Spartan devices) a single XADC analog-to-digital converter, which is an improved and renamed version of Virtex-6 system monitor
• Miscellaneous configuration logic: like Virtex-6

Depending on exact device family, devices may also contain some special blocks:

• GTP multi-gigabit transceivers, ^[70] with speed range of 500 Mb/s to 6.6 Gb/s and parallel width of 8 or 16 bits (10 or 20 in 8b/10b bypass mode)
• GTX multi-gigabit transceivers, ^[71] with speed range of 500 Mb/s to 12.5 Gb/s and parallel width of 8, 16, or 32 bits (10, 20, or 40 in 8b/10b bypass mode)
• GTH multi-gigabit transceivers, with speed range of 500 Mb/s to 13.1 Gb/s and parallel width of 8, 16, or 32 bits (10, 20, or 40 in 8b/10b bypass mode)
• GTZ multi-gigabit transceivers, with speed range of up to 28.05 Gb/s and parallel width of up to 128 bits (160 in 8b/10b bypass mode). The GTZ transceivers, when present, reside on a separate die from the main FPGA. The documentation for GTZ transceivers is not publicly available, being restricted to members of Xilinx GTZ Lounge.
• embedded PCI Express cores capable of Gen2 ×8 operation
• embedded PCI Express cores capable of Gen3 ×8 operation
• (Zynq-7000 devices) a PS (processing system) block, ^[72] containing a system on chip based on ARM Cortex-A9

Model	Family	CLBs	6-LUTs (=CLBs×8)	SLICEMs	Block RAMs (36kbit each)	DSP48E1 blocks	CMTs	Clock Regions	I/O banks (max)	User I/Os (max)	Gigabit transceivers (max)	PCI Express Cores	XADCs	Processing System	Notes
XC7S6	Spartan-7	469*	3752*	280*	5*	10*	2	2 (2x1)	2 HR	100 HR	-	-	-	-	software-limitted version of XC7S15
XC7S15	Spartan-7	1000	8000	600	10	20	2	2 (2x1)	2 HR	100 HR	-	-	-	-
XC7S25	Spartan-7	1825	14600	1250	45	80	3	4 (2x2)	3 HR	150 HR	-	-	1	-	XC7A25T with disabled transceivers
XC7S50	Spartan-7	4075	32600	2400	75	120	5	6 (2x3)	5 HR	250 HR	-	-	1	-	XC7A50T with disabled transceivers
XC7S75	Spartan-7	6000*	48000*	3328*	90*	140*	8	8 (2x4)	8 HR	400 HR	-	-	1	-	software-limitted version of XC7S100
XC7S100	Spartan-7	8000	64000	4400	120	160	8	8 (2x4)	8 HR	400 HR	-	-	1	-
XC7A12T	Artix-7	1000*	8000*	684*	20*	40*	3	4 (2x2)	3 HR	150 HR	2 GTP	1 Gen2×4	1	-	software-limitted version of XC7A25T
XC7A15T	Artix-7	1300*	10400*	800*	25*	45*	5	6 (2x3)	5 HR	250 HR	4 GTP	1 Gen2×4	1	-	software-limitted version of XC7A50T
XC7A25T	Artix-7	1825	14600	1250	45	80	3	4 (2x2)	3 HR	150 HR	4 GTP	1 Gen2×4	1	-
XC7A35T	Artix-7	2600*	20800*	1600*	50*	90*	5	6 (2x3)	5 HR	250 HR	4 GTP	1 Gen2×4	1	-	software-limitted version of XC7A50T
XC7A50T	Artix-7	4075	32600	2400	75	120	5	6 (2x3)	5 HR	250 HR	4 GTP	1 Gen2×4	1	-
XC7A75T	Artix-7	5900*	47200*	3568*	105*	180*	6	8 (2x4)	6 HR	300 HR	8 GTP	1 Gen2×4	1	-	software-limitted version of XC7A100T
XC7A100T	Artix-7	7925	63400	4750	135	240	6	8 (2x4)	6 HR	300 HR	8 GTP	1 Gen2×4	1	-
XC7A200T	Artix-7	16825	134600	11550	365	740	10	10 (2x5)	10 HR	500 HR	16 GTP	1 Gen2×4	1	-
XC7K70T	Kintex-7	5125	41000	3350	135	240	6	8 (2x4)	4 HR + 2 HP	200 HR + 100 HP	8 GTX	1 Gen2×8	1	-
XC7K160T	Kintex-7	12675	101400	8750	325	600	8	10 (2x5)	5 HR + 3 HP	250 HR + 150 HP	8 GTX	1 Gen2×8	1	-
XC7K325T	Kintex-7	25475	203800	16000	445	840	10	14 (2x7)	7 HR + 3 HP	350 HR + 150 HP	16 GTX	1 Gen2×8	1	-
XC7K355T	Kintex-7	27825	222600	20350	715	1440	6	12 (2x6)	6 HR	300 HR	24 GTX	1 Gen2×8	1	-
XC7K410T	Kintex-7	31775	254200	22650	795	1540	10	14 (2x7)	7 HR + 3 HP	350 HR + 150 HP	16 GTX	1 Gen2×8	1	-
XC7K420T	Kintex-7	32575*	260600*	23752*	835*	1680*	8	16 (2x8)	8 HR	400 HR	32 GTX	1 Gen2×8	1	-	software-limitted version of XC7K480T
XC7K480T	Kintex-7	37325	298600	27150	955	1920	8	16 (2x8)	8 HR	400 HR	32 GTX	1 Gen2×8	1	-
XC7V585T	Virtex-7	45525	364200	27750	795	1260	18	18 (2x9)	3 HR + 15 HP	100 HR + 750 HP	36 GTX	3 Gen2×8	1	-
XC7V2000T	Virtex-7	152700	1221600	86200	1292	2160	24	24 (2x12)	24 HP	1200 HP	36 GTX	4 Gen2×8	1	-	3D device, made of 4 identical FPGA die
XC7VX330T	Virtex-7	25500	204000	17550	750	1120	14	14 (2x7)	1 HR + 13 HP	50 HR + 650 HP	28 GTH	2 Gen3×8	1	-
XC7VX415T	Virtex-7	32200	257600	26100	880	2160	12	12 (2x6)	12 HP	600 HP	48 GTH	2 Gen3×8	1	-
XC7VX485T	Virtex-7	37950	303600	32700	1030	2800	14	14 (2x7)	14 HP	700 HP	56 GTX	4 Gen2×8	1	-
XC7VX550T	Virtex-7	43300*	346400*	34900*	1180*	2880*	20	20 (2x10)	20 HP	600 HP	80 GTH	2 Gen3×8	1	-	software-limitted version of XC7VX690T
XC7VX690T	Virtex-7	54150	433200	43550	1470	3600	20	20 (2x10)	20 HP	1000 HP	80 GTH	3 Gen3×8	1	-
XC7VX980T	Virtex-7	76500	612000	55350	1500	3600	18	18 (2x9)	18 HP	900 HP	72 GTH	3 Gen3×8	1	-
XC7VX1140T	Virtex-7	109400	875200	70800	1880	3360	24	24 (2x12)	24 HP	1100 HP	96 GTH	4 Gen3×8	1	-	3D device, made of 4 identical FPGA die
XC7VH580T	Virtex-7	54700	437600	35400	940	1680	12	12 (2x6)	12 HP	600 HP	48 GTH + 8 GTZ	2 Gen3×8	1	-	heterogenous 3D device, made of 2 FPGA die (identical to the XC7VX1140T FPGA die) and 1 GTZ die
XC7VH870T	Virtex-7	82050	656400	53100	1410	2520	18	18 (2x9)	18 HP	300 HP	72 GTH + 16 GTZ	3 Gen3×8	1	-	heterogenous 3D device, made of 3 FPGA die (identical to the XC7VX1140T FPGA die) and 2 GTZ die
XC7Z007S	Zynq-7000 (Artix-7 FPGA fabric) [73]	1800*	14400*		50*	66*	2	4 (2x2)	2 HR	100 HR	-	-	1	single core	software-limitted XC7Z010 with one ARM core disabled
XC7Z012S	Zynq-7000 (Artix-7 FPGA fabric)	4300*	34400*		72*	120*	3	6 (2x3)	3 HR	150 HR	4 GTP	1 Gen2×4	1	single core	software-limitted XC7Z015 with one ARM core disabled
XC7Z014S	Zynq-7000 (Artix-7 FPGA fabric)	5075*	40600*		107*	170*	4	6 (2x3)	4 HR	200 HR	-	-	1	single core	software-limitted XC7Z020 with one ARM core disabled
XC7Z010	Zynq-7000 (Artix-7 FPGA fabric)	2200	17600	1500	60	80	2	4 (2x2)	2 HR	100 HR	-	-	1	dual core
XC7Z015	Zynq-7000 (Artix-7 FPGA fabric)	5775	46200	3600	95	160	3	6 (2x3)	3 HR	150 HR	4 GTP	1 Gen2×4	1	dual core
XC7Z020	Zynq-7000 (Artix-7 FPGA fabric)	6650	53200	4350	140	220	4	6 (2x3)	4 HR	200 HR	-	-	1	dual core
XC7Z030	Zynq-7000 (Kintex-7 FPGA fabric)	9825	78600	6650	265	400	5	8 (2x4)	2 HR + 3 HP	100 HR + 150 HP	4 GTX	1 Gen2×4	1	dual core
XC7Z035	Zynq-7000 (Kintex-7 FPGA fabric)	21487.5*	171900*		500*	900	8	14 (2x7)	5 HR + 3 HP	212 HR + 150 HP	8 GTX	1 Gen2×8	1	dual core	software-limitted version of XC7Z045
XC7Z045	Zynq-7000 (Kintex-7 FPGA fabric)	27325	218600	17600	545	900	8	14 (2x7)	5 HR + 3 HP	212 HR + 150 HP	8 GTX	1 Gen2×8	1	dual core
XC7Z100	Zynq-7000 (Kintex-7 FPGA fabric)	34675	277400	27050	755	2020	8	14 (2x7)	5 HR + 3 HP	250 HR + 150 HP	16 GTX	1 Gen2×8	1	dual core

Note: many 7 series devices are actually software-limitted versions of larger devices: ^[74] for example, XC7A35T is the exact same die as XC7A50T, with the same geometry and block count, but the Xilinx development tools artificially limit device usage to the limits in the table above. Such software-limitted devices have very different behavior from "full" devices when nearing full utilization: a design that would have utilized 90% of XC7A50T resources will most likely fail to route (or succeed with very suboptimal performance), since the place&route tool will have very little space to optimally arrange blocks and will likely run out of routing resources due to suboptimal placement. However, an XC7A35T design that utilizes even 100% of its resources will almost certainly route with no performance degradation, as it is far from the real hardware limits, and the placer has full freedom to utilize any subset of the available blocks as long as the total used CLB/DSP/block RAM count is within the allowed software limit. The software-enforced limits are marked with * in the above table.

Note: some Spartan-7 devices are identical to some Artix-7 devices, but with disabled transceivers. However, this is different from the above software-enforced usage limit: the transceivers cannot be used anyway, as their power and I/O pads are not bonded out to device pins in the packaging.

Note: the Artix-7 devices use the same PCI Express block as Kintex-7 devices, with Gen2×8 support, but they can only be used in at most Gen2×4 configuration due to GTP transceiver limitations.

Note: several devices have smaller max User I/Os count than the I/O bank count would imply. This means that the device is not available in any packaging that actually bonds out the complete set of pads.

UltraScale and UltraScale+

The UltraScale devices are made of: ^[75]

• CLBs (configurable logic blocks), which are a modified version of the 7 Series CLB:
  • every CLB now contains exactly one SLICE, which can be a SLICEM or a SLICEL
  • every SLICE now contains 8 6-input LUTs, 16 flip-flops, a carry chain, and 3-level tree of wide LUT multiplexers, making it roughly equivalent to two 7 Series SLICEs (and retaining the rough logic capacity of a single CLB)
  • because of the higher wide LUT multiplexer tree, the LUTs within a SLICE can now be combined up to a single 9-input LUT
  • the available distributed RAM combinations within a SLICEM are now:
    • 32×16, 64×8, 128×4, 256×2, 512×1 single port RAM
    • 32×8, 64×4, 128×2, 256×1 dual port RAM
    • 32×4, 64×2, 128×1 quad port RAM
    • 32×2, 64×1 octal port RAM
    • 32×14, 64×7 simple dual port RAM
• 36kbit splittable true dual block RAMs, with some minor upgrades compared to 7 Series
• DSP48E2 blocks, with some minor upgrades compared to 7 Series DSP48E1 blocks
• I/O banks with CMTs: with major changes from 7 Series ^[76]
  • banks still come in HR and HP kinds
  • each bank has 52 I/O pins: 24 differential pairs, and 4 unpaired pins
  • the bank is split into 4 byte groups, each made of 6 differential pairs and one unpaired pin
  • each byte group is further split into a lower nibble (with 3 differential pairs) and upper nibble (with 3 differential pairs and one unpaired pin)
  • the ISERDES/OSERDES blocks are replaced with BITSLICE blocks; there is one TX BITSLICE and one RX bitslice for every pin, plus an additional TX bitslice for every nibble that can control the tristate signal for all pins in a nibble
  • each bank has a CMT, with one MMCM and two PLLs
  • added MIPI D-PHY support
• much more complex, distributed global clock network split into clock regions
• system monitors, which is once again a renamed version of 7 Series XADC. There is one system monitor per FPGA die (ie. multi-die FPGAs have multiple system monitors).
• Miscellaneous configuration logic
• GTH multi-gigabit transceivers with speed up to 16.3 Gb/s and parallel width of 16, 32, or 64 bits (20, 40, or 80 bits in 8b/10b bypass mode)
• (on some devices) GTY multi-gigabit transceivers with speed up to 30.5 Gb/s and parallel width of 16, 32, 64, or 128 bits (20, 40, 80, or 160 bits in 8b/10b bypass mode)
• embedded PCI Express cores capable of Gen3 ×8 operation
• (on some devices) 100 Gigabit Ethernet MAC
• (on some devices) embedded Interlaken core

The UltraScale+ devices have a few differences:

• HR banks no longer exist, being replaced with a new kind of I/O banks: HD (High Density) banks, which are very different to HR banks:
  • 24 pins (12 differential pairs) per bank
  • no CMT
  • no SERDES or BITSLICE blocks; the only logic available is simple flip-flops or DDR registers
• upgraded MMCM and PLL
• upgraded GTH transceivers
• upgraded GTY transceivers with speed up to 32.75 Gb/s
• some devices have GTM transceivers with speed up to 58.0 Gb/s (using PAM4 encoding) and parallel width of 16, 32, 64, or 128 bits (20, 40, 80, or 160 bits in 8b/10b bypass mode)
• new PCI Express cores:
  • PCIE4 core capable of Gen3 ×16 or Gen4 ×8 operation
  • PCIE4C core, additionally capable of CCIX protocol
• some devices have new UltraRAM blocks, which are true dual port 288kbit RAMs, in 4096×72 configuration

Zynq UltraScale+ devices are ARM Cortex-A53 based systems on chip sharing a die with an FPGA. The SoC part of the device is called a Processing System (PS). Each model of Zynq UltraScale+ MPSoC is available in up to 3 sub-models: CG, EG, and EV. The main differences among these sub-models are in the CPU and GPU configurations. ^[77] Zynq UltraScale+ RFSoC devices are available in DR sub-models, which have PS capabilities identical to MPSoC EG sub-models.

	CG	EG and DR	EV
APU	2x Arm A53	4x Arm A53	4x Arm A53
RPU	2x Arm R5	2x Arm R5	2x Arm R5
GPU	-	Arm Mali-400MP2	Arm Mali-400MP2
VCU	-	-	H.264/H.265

Zynq UltraScale+ devices have some additional blocks:

• (some RFSoC devices) SD-FEC cores
• (some RFSoC devices) Digital Front End subsystem (a set of hard logic blocks for RF signal processing)
• (RFSoC devices) high-speed (radio frequency) analog-to-digital converters (RF-ADC) and digital-to-analog converters (RF-DAC), for 5G applications
• (MPSoC EV devices) a video codec unit (VCU) performing H.264 and H.265 decoding/encoding

Model	Family	CLBs	6-LUTs (=CLBs×8)	SLICEMs	Block RAMs (36kbit each)	Ultra RAMs (288kbit each)	DSP48E2 blocks	CMTs	Clock Regions	I/O banks (max)	User I/Os (max)	Gigabit transceivers (max)	PCI Express Cores	100 Gigabit Ethernet MACs	Intelaken Cores	Others	Notes
XCKU025	Kintex UltraScale	18180	145440	8460	360	-	1152	6	12 (4×3)	2 HR + 4 HP	104 HR + 208 HP	12 GTH	1	-	-	-	cut (partial) version of XCKU040
XCKU035	Kintex UltraScale	25391*	203128*		540*	-	1700*	10	20 (4×5)	2 HR + 8 HP	104 HR + 416 HP	16 GTH	2*	-	-	-	software-limitted version of XCKU040
XCKU040	Kintex UltraScale	30300	242400	14100	600	-	1920	10	20 (4×5)	2 HR + 8 HP	104 HR + 416 HP	20 GTH	3	-	-	-
XCKU060	Kintex UltraScale	41460	331680	18360	1080	-	2760	12	30 (6×5)	2 HR + 10 HP	104 HR + 520 HP	32 GTH	3	-	-	-
XCKU085	Kintex UltraScale	62190*	497520*		1620*	-	4100*	22	54 (6×9)	4 HR + 18 HP	104 HR + 572 HP	56 GTH	4*	-	-	-	software-limitted version of XCKU115 with one partial die
XCKU095	Kintex UltraScale	67200	537600	9600	1680*	-	768	16	40 (5×8)	1 HR + 15 HP	52 HR + 650 HP	32 GTH + 32 GTY	4	2*	2*	-	software-limitted version of XCVU095
XCKU115	Kintex UltraScale	82920	663360	36720	2160	-	5520	24	60 (6×10)	4 HR + 20 HP	156 HR + 676 HP	64 GTH	6	-	-	-	a multi-die FPGA made of two XCKU060
XCVU065	Virtex UltraScale	44760	358080	9660	1260	-	600	10	30 (6×5)	1 HR + 9 HP	52 HR + 468 HP	20 GTH + 20 GTY	2	3	3	-
XCVU080	Virtex UltraScale	55714*	445712*		1421*	-	672*	16	40 (5×8)	1 HR + 15 HP	52 HR + 780 HP	32 GTH + 32 GTY	4	4	6	-	software-limitted version of XCVU095
XCVU095	Virtex UltraScale	67200	537600	9600	1728	-	768	16	40 (5×8)	1 HR + 15 HP	52 HR + 780 HP	32 GTH + 32 GTY	4	4	6	-
XCVU125	Virtex UltraScale	89520	716160	19320	2520	-	1200	20	60 (6×10)	2 HR + 18 HP	104 HR + 780 HP	40 GTH + 40 GTY	4	6	6	-	a multi-die FPGA made of two XCVU065
XCVU160	Virtex UltraScale	115800*	926400*		3276*	-	1560*	28	84 (6×14)	2 HR + 26 HP	52 HR + 650 HP	52 GTH + 52 GTY	4*	9	8	-	software-limitted version of XCVU190 with one partial die
XCVU190	Virtex UltraScale	134280	1074240	28980	3780	-	1800	30	90 (6×15)	3 HR + 27 HP	52 HR + 650 HP	60 GTH + 60 GTY	6	9	9	-	a multi-die FPGA made of three XCVU065
XCVU440	Virtex UltraScale	316620	2532960	57420	2520	-	2880	30	135 (9×15)	3 HR + 27 HP	52 HR + 1404 HP	48 GTH	6	3	-	-	a multi-die FPGA made of three dedicated die
XCAU7P	Artix UltraScale+	4680	37440		108		215	2		2 HP + 6 HD	104 HP + 144 HD	4 GTH	1 PCIE4C	-	-	-	not yet in production
XCAU10P	Artix UltraScale+	5500*	44000*		100*	-	400	3	6 (2x3)	3 HP + 3 HD	156 HP + 72 HD	12 GTH	1 PCIE4C	-	-	-	software-limitted version of XCAU15P
XCAU15P	Artix UltraScale+	9720	77760	5040	144	-	576	3	6 (2x3)	3 HP + 3 HD	156 HP + 72 HD	12 GTH	1 PCIE4C	-	-	-
XCAU20P	Artix UltraScale+	13625*	109000*		200*	-	900*	3*	16 (4x4)	3 HP + 3 HD	156 HP + 72 HD	12 GTY	1 PCIE4	-	-	-	software-limitted version of XCKU5P
XCAU25P	Artix UltraScale+	17625*	141000*		300*	-	1200*	4	16 (4x4)	4 HP + 4 HD	208 HP + 96 HD	12 GTY	1 PCIE4	-	-	-	software-limitted version of XCKU5P
XCKU3P	Kintex UltraScale+	20340*	162720*		360*	48*	1368*	4	16 (4×4)	4 HP + 4 HD	208 HP + 96 HD	16 GTY	1 PCIE4	-	-	-	software-limitted version of XCKU5P
XCKU5P	Kintex UltraScale+	27120	216960	12480	480	64	1824	4	16 (4×4)	4 HP + 4 HD	208 HP + 96 HD	16 GTY	1 PCIE4	1	-	-
XCKU9P	Kintex UltraScale+	34260	274080	18000	912	-	2520	4	25 (4×7-3)	4 HP + 5 HD	208 HP + 96 HD	28 GTH	-	-	-	-	same die as XCZU9*, with disabled PS
XCKU11P	Kintex UltraScale+	37320	298560	18540	600	80	2928	8	29 (4×8-3)	8 HP + 4 HD	416 HP + 96 HD	32 GTH + 20 GTY	4 PCIE4	2	1	-	same die as XCZU11*, with disabled PS
XCKU13P	Kintex UltraScale+	42660	341280	23040	744	112	3528	4	25 (4×7-3)	4 HP + 5 HD	208 HP + 96 HD	28 GTH	-	-	-	-	same die as XCZU15*, with disabled PS
XCKU15P	Kintex UltraScale+	65340	522720	20160	984	128	1968	11	41 (4×11-3)	11 HP + 4 HD	572 HP + 96 HD	44 GTH + 32 GTY	5 PCIE4	4	4	-	same die as XCZU19*, with disabled PS
XCKU19P	Kintex UltraScale+	105300	842400		1728	288	1080	9	45 (5×9)	9 HP + 3 HD	468 HP + 72 HD	32 GTY	3 PCIE4C	1	-	-	partial version of XCVU23P
XCVU3P	Virtex UltraScale+	49260	394080	24660	720	320	2280	10	30 (6×5)	10 HP	520 HP	40 GTY	2 PCIE4	3	3	-
XCVU5P	Virtex UltraScale+	75072.125*	600577*		1024*	470*	3474*	20	60 (6×10)	20 HP	832 HP	80 GTY	4 PCIE4	4*	4*	-	software limited version of XCVU7P
XCVU7P	Virtex UltraScale+	98520	788160	49320	1440	640	4560	20	60 (6×10)	20 HP	832 HP	80 GTY	4 PCIE4	6	6	-	a multi-die FPGA made of two XCVU3P FPGAs
XCVU9P, XCU200	Virtex UltraScale+	147780	1182240	75120	2160	960	6840	30	90 (6×15)	30 HP	832 HP	120 GTY	6 PCIE4	9	9	-	a multi-die FPGA made of three XCVU3P FPGAs; XCU200 is the designation of the FPGA used on the Alveo U200 board, which is rebadged XCVU9P
XCVU11P	Virtex UltraScale+	162000	1296000	74160	2016	960	9216	12	96 (8×12)	12 HP	624 HP	96 GTY	3 PCIE4	9	6	-	a multi-die FPGA made of three die
XCVU13P, XCU250	Virtex UltraScale+	216000	1728000	98880	2688	1280	12288	16	128 (8×16)	16 HP	832 HP	128 GTY	4 PCIE4	12	8	-	a multi-die FPGA made of four die (same base die as XCVU11P); XCU250 is the designation of the FPGA used on the Alveo U250 board, which is rebadged XCVU13P
XCVU19P	Virtex UltraScale+	510720	4085760	119520	2160	320	3840	40	180 (9×20)	40 HP + 4 HD	1976 HP + 96 HD	80 GTY	8 PCIE4C	-	-	-	a multi-die FPGA made of four die
XCVU23P, XCU26	Virtex UltraScale+	128700	1029600	29040	2112	352	1320	11	55 (5×11)	11 HP + 3 HD	572 HP + 72 HD	34 GTY + 4 GTM	4 PCIE4C	2	-	-	XCU26 is the designation of the FPGA used on the Alveo SN1022 SmartNIC board, which is a rebadged XCVU23P
XCVU27P	Virtex UltraScale+	162000*	1296000*	74160*	2016*	960*	9216*	16	128 (8×16)	16 HP	676 HP	32 GTY + 48 GTM	1 PCIE4	15	8	-	software-limitted version of XCVU29P
XCVU29P	Virtex UltraScale+	216000	1728000	98880	2688	1280	12288	16	128 (8×16)	16 HP	676 HP	32 GTY + 48 GTM	1 PCIE4	15	8	-	a multi-die FPGA made of four die; one die is identical to the one used in XCVU11P, the other three contain the GTM transceivers
XCVU31P	Virtex UltraScale+ HBM	54960	439680	25680	672	320	2880	4	32 (8×4)	4 HP	208 HP	32 GTY	4 PCIE4C	2	-	HBM memory controller + 4GB HBM memory stack	same die as XCVU33P, but with less HBM memory
XCVU33P	Virtex UltraScale+ HBM	54960	439680	25680	672	320	2880	4	32 (8×4)	4 HP	208 HP	32 GTY	4 PCIE4C	2	-	2 HBM memory controllers + 2×4GB HBM memory stacks
XCVU35P, XCU50	Virtex UltraScale+ HBM	108960	871680	50400	1344	640	5952	8	64 (8×8)	8 HP	416 HP	64 GTY	1 PCIE4 + 4 PCIE4C	5	2	2 HBM memory controllers + 2×4GB HBM memory stacks	a multi-die FPGA made of XCVU33P + one XCVU11P die; XCU50 is the designation of the FPGA used on the Alveo U50 board, which is rebadged XCVU35P
XCVU37P, XCU280, XCU55C	Virtex UltraScale+ HBM	162960	1303680	75120	2016	960	9024	12	96 (8×12)	12 HP	624 HP	96 GTY	2 PCIE4 + 4 PCIE4C	8	4	2 HBM memory controllers + 2×4GB HBM memory stacks	a multi-die FPGA made of XCVU33P + two XCVU11P die; XCU280 and XCU55C are the designations of the FPGAs used on the Alveo U280 and Alveo U55C boards, respectively, which are rebadged XCVU37P
XCVU45P	Virtex UltraScale+ HBM	108960	871680	50400	1344	640	5952	8	64 (8×8)	8 HP	416 HP	64 GTY	1 PCIE4 + 4 PCIE4C	5	2	2 HBM memory controllers + 2×8GB HBM memory stacks	same as XCVU35P, but with more HBM memory
XCVU47P	Virtex UltraScale+ HBM	162960	1303680	75120	2016	960	9024	12	96 (8×12)	12 HP	624 HP	96 GTY	2 PCIE4 + 4 PCIE4C	8	4	2 HBM memory controllers + 2×8GB HBM memory stacks	same as XCVU37P, but with more HBM memory
XCVU57P	Virtex UltraScale+ HBM	162960	1303680	75120	2016	960	9024	12	96 (8×12)	12 HP	624 HP	32 GTY + 32 GTM	4 PCIE4C	10	4	2 HBM memory controllers + 2×8GB HBM memory stacks	same as XCVU47P, but with the XCVU11P die replaced with XCVU27P GTM-containing die
XCZU1CG, XCZU1EG	Zynq UltraScale+ MPSoC	4680	37440		108	-	216	3	3 (1×3)	3 HP + 1 HD	156 HP + 24 HD	-	-	-	-	Processing System
XCZU2CG, XCZU2EG	Zynq UltraScale+ MPSoC	5904*	47232*		150*	-	240*	3	6 (2×3)	3 HP + 4 HD	156 HP + 96 HD	-	-	-	-	Processing System	software-limitted XCZU3
XCZU3CG, XCZU3EG	Zynq UltraScale+ MPSoC	8820	70560	3600	216	-	360	3	6 (2×3)	3 HP + 4 HD	156 HP + 96 HD	-	-	-	-	Processing System
XCZU3TCG XCZU3TEG	Zynq UltraScale+ MPSoC	9000	72000		144	48	576	1		1 HP + 3 HD	52 HP + 72 HD	8 GTH	1 PCIE4C	-	-	Processing System	not yet in production
XCZU4CG, XCZU4EG, XCZU4EV	Zynq UltraScale+ MPSoC	10980*	87840*		128*	48*	728*	4	12 (3×4)	4 HP + 4 HD	156 HP + 96 HD	16 GTH	2 PCIE4	-	-	Processing System, VCU	software-limitted XCZU5
XCZU5CG, XCZU5EG, XCZU5EV, XCK26	Zynq UltraScale+ MPSoC	14640	117120	7200	144	64	1248	4	12 (3×4)	4 HP + 4 HD	156 HP + 96 HD	16 GTH	2 PCIE4	-	-	Processing System, VCU	XCK26 is the designation of the device on the Kria K26 system on module, which is a rebadged XCZU5EV device
XCZU6CG, XCZU6EG	Zynq UltraScale+ MPSoC	26825.5*	214604*		714*	-	1973*	4	25 (4×7-3)	4 HP + 5 HD	208 HP + 120 HD	24 GTH	-	-	-	Processing System	software-limitted XCZU9
XCZU7CG, XCZU7EG, XCZU7EV, XCU30	Zynq UltraScale+ MPSoC	28800	230400	12720	312	96	1728	8	20 (4×6-4)	8 HP + 4 HD	416 HP + 48 HD	24 GTH	2 PCIE4	-	-	Processing System, VCU	XCU30 is the designation of the devices on the Alveo U30 board, which are rebadged XCZU7EV devices
XCZU9CG, XCZU9EG	Zynq UltraScale+ MPSoC	34260	274080	18000	912	-	2520	4	25 (4×7-3)	4 HP + 5 HD	208 HP + 120 HD	24 GTH	-	-	-	Processing System
XCZU11EG	Zynq UltraScale+ MPSoC	37320	298560	18540	600	80	2928	8	29 (4×8-3)	8 HP + 4 HD	416 HP + 96 HD	32 GTH + 16 GTY	4 PCIE4	2	1	Processing System
XCZU15EG	Zynq UltraScale+ MPSoC	42660	341280	23040	744	112	3528	4	25 (4×7-3)	4 HP + 5 HD	208 HP + 120 HD	24 GTH	-	-	-	Processing System
XCZU17EG	Zynq UltraScale+ MPSoC	52925.375*	423403*		796*	102*	1590*	11	41 (4×11-3)	11 HP + 4 HD	572 HP + 96 HD	44 GTH + 28 GTY	4* PCIE4	2*	2*	Processing System	software-limitted XCZU19
XCZU19EG, XCU25	Zynq UltraScale+ MPSoC	65340	522720	20160	984	128	1968	11	41 (4×11-3)	11 HP + 4 HD	572 HP + 96 HD	44 GTH + 28 GTY	5 PCIE4	4	4	Processing System	XCU25 is the designation of the device on the Alveo U25 board, which is a rebadged XCZU19EG device
XCZU21DR	Zynq UltraScale+ RFSoC	53160	425280	26700	1080	80	4272	8	45 (6×8-3)	8 HP + 6 HD	208 HP + 72 HD	16 GTY	2 PCIE4	2	1	Processing System, 8 SD-FEC cores	same die as XCZU28DR
XCZU25DR	Zynq UltraScale+ RFSoC	38761*	310088*	19561*	792*	48*	3145*	6	33 (6×6-3)	6 HP + 4 HD	299 HP + 48 HD	8 GTY	1 PCIE4	1	1	Processing System, 8×4GSPS RF-ADC, 8×6.5GSPS RF-DAC	partial XCZU28DR die
XCZU27DR	Zynq UltraScale+ RFSoC	53160	425280	26700	1080	80	4272	8	45 (6×8-3)	8 HP + 6 HD	299 HP + 48 HD	16 GTY	2 PCIE4	2	1	Processing System, 8×4GSPS RF-ADC, 8×6.5GSPS RF-DAC	same die as XCZU28DR
XCZU28DR	Zynq UltraScale+ RFSoC	53160	425280	26700	1080	80	4272	8	45 (6×8-3)	8 HP + 6 HD	299 HP + 48 HD	16 GTY	2 PCIE4	2	1	Processing System, 8×4GSPS RF-ADC, 8×6.5GSPS RF-DAC, 8 SD-FEC cores
XCZU29DR	Zynq UltraScale+ RFSoC	53160	425280	26700	1080	80	4272	8	45 (6×8-3)	8 HP + 6 HD	312 HP + 96 HD	16 GTY	2 PCIE4	2	1	Processing System, 16×2GSPS RF-ADC, 16×6.5GSPS RF-DAC	same die as XCZU28DR
XCZU39DR	Zynq UltraScale+ RFSoC	53160	425280	26700	1080	80	4272	8	45 (6×8-3)	8 HP + 6 HD	312 HP + 96 HD	16 GTY	2 PCIE4	2	1	Processing System, 16×2.2GSPS RF-ADC, 16×6.5GSPS RF-DAC	same die as XCZU28DR
XCZU42DR	Zynq UltraScale+ RFSoC	27960	223680	13740	648	160	1872	5	22 (5x5-3)	5 HP + 1 HD	128 HP + 24 HD	8 GTY	-	1	-	Processing System, 2×5GSPS RF-ADC, 8×2.5GSPS RF-ADC, 8×10GSPS RF-DAC	same die as XCZU67DR
XCZU43DR	Zynq UltraScale+ RFSoC	53160	425280	26700	1080	80	4272	8	45 (6×8-3)	8 HP + 6 HD	299 HP + 48 HD	16 GTY	2 PCIE4C	2	1	Processing System, 4×5GSPS RF-ADC, 4×10GSPS RF-DAC	same die as XCZU48DR
XCZU46DR	Zynq UltraScale+ RFSoC	53160	425280	26700	1080	80	4272	8	45 (6×8-3)	8 HP + 6 HD	312 HP + 48 HD	16 GTY	2 PCIE4C	2	1	Processing System, 4×5GSPS RF-ADC, 8×2.5GSPS RF-ADC 12×10GSPS RF-DAC, 8 SD-FEC cores	same die as XCZU48DR
XCZU47DR	Zynq UltraScale+ RFSoC	53160	425280	26700	1080	80	4272	8	45 (6×8-3)	8 HP + 6 HD	299 HP + 48 HD	16 GTY	2 PCIE4C	2	1	Processing System, 8×5GSPS RF-ADC, 8×10GSPS RF-DAC	same die as XCZU48DR
XCZU48DR	Zynq UltraScale+ RFSoC	53160	425280	26700	1080	80	4272	8	45 (6×8-3)	8 HP + 6 HD	299 HP + 48 HD	16 GTY	2 PCIE4C	2	1	Processing System, 8×5GSPS RF-ADC, 8×10GSPS RF-DAC, 8 SD-FEC cores
XCZU49DR	Zynq UltraScale+ RFSoC	53160	425280	26700	1080	80	4272	8	45 (6×8-3)	8 HP + 6 HD	312 HP + 96 HD	16 GTY	2 PCIE4C	2	1	Processing System, 16×2.5GSPS RF-ADC, 16×10GSPS RF-DAC	same die as XCZU48DR
XCZU65DR	Zynq UltraScale+ RFSoC	27960	223680	13740	648	160	1872	5	22 (5x5-3)	5 HP + 1 HD	128 HP + 24 HD	8 GTY	-	1	-	Processing System, Digital Front End, 6×5.9GSPS RF-ADC, 6×10GSPS RF-DAC	same die as XCZU67DR
XCZU67DR	Zynq UltraScale+ RFSoC	27960	223680	13740	648	160	1872	5	22 (5x5-3)	5 HP + 1 HD	128 HP + 24 HD	8 GTY	-	1	-	Processing System, Digital Front End, 2×5.9GSPS RF-ADC, 8×2.95GSPS RF-ADC, 8×10GSPS RF-DAC

Note: the clock region grid is irregular on some UltraScale+ devices because of a hole in bottom for the Processing System (and possibly the VCU).

Versal

In 2018, Xilinx announced a product line called Versal. ^[78] Versal chips contain CPU, GPU, DSP, and FPGA components. Versal is fabricated using 7nm process technology.

The Versal devices are made of: ^[79]

• PMC (Platform Management Controller), a MicroBlaze-based processor block responsible for booting the device and monitoring its operations
• PS (Processing System), an ARM system on a chip block with dual core Cortex-A72 (APU) and dual-core Cortex-R5F (RPU)
• (on some devices) CPM, a hard PCI Express block with CCIX support; comes in Gen4 and Gen5 version
• (on some devices) XRAM, a single 32Mbit block of static RAM
• a NoC (Network on Chip) spanning the device, with AXI4 interface blocks, connecting the PS, the CPM, the FPGA, the DDRMC cores, and the AI cores together
• one or more DDRMC (DDR memory controller) blocks
• (on some devices) HBM memory controller blocks
• XPIO I/O banks, which are the successor to UltraScale+ HP I/O banks; in a departure from previous devices, the XPIO banks are considered to be outside the FPGA part, and some XPIO banks can only be used by the DDRMC blocks (without FPGA connectivity)
• GTY transceivers, which can be used by the FPGA or by the CPM
• GTYP transceivers, which are a minor improvement of GTY transceivers
• GTM transceivers
• the FPGA fabric with:
  • configurable logic blocks (CLBs), which are quite different to previous architectures
    • a CLB is made of 4 SLICEs: 2 SLICELs and 2 SLICEMs
    • each SLICE still contains 8 6-input LUTs, each fracturable into two 5-input LUTs with shared inputs
    • each slice still contains 16 flip-flops, two for each LUT
    • there are no more wide LUT multiplexers
    • the carry chain has been replaced with new carry and cascade logic
    • the distributed RAM configurations are different
  • 36kbit true dual port block RAMs, with some changes from UltraScale+
  • 288kbit UltraRAM blocks, with some changes from UltraScale+
  • DSP58 blocks, which replace the old DSP48* blocks; two adjacent DSP58 blocks can be combined into a single DSP58_CPLX block, performing complex arithmetic
  • HD I/O blocks, similar to UltraScale+
    • now with 11 differential pairs (22 pins) per block
  • NoC master access ports
  • NoC slave access ports
  • hard IP blocks:
    • PCI Express Gen4 and Gen5 cores
    • MRMAC (Multirate Ethernet MAC), usable in 1×100Gbit, 2×50Gbit, 1×40Gbit, 4×25Gbit, 4×10Gbit configurations
    • DCMAC (600G Channelized Multirate Ethernet Subsystem), usable in 1×400Gbit, 3×200Gbit, 6×100Gbit configurations
    • 600Gbit Interlaken block, usable in 12×56.42Gbit, 24×28.21Gbit, or 24×12.5Gbit configurations
    • 400Gbit HSC (High-Speed Crypto) Engine, usable in 1×400Gbit, 2×200Gbit, or 4×100Gbit configurations
    • VDE (Video Decoder Engine)
• (on some devices) AI Engines, vector processor cores meant for machine learning usage
• (on some devices) AI-ML Engines, updated version of the AI Engines

Model	Family	SLICEs	6-LUTs (=SLICEs×8)	Block RAMs (36kbit each)	Ultra RAMs (288kbit each)	DSP58 blocks	DDRMC blocks	XPIO banks	HDIO banks	NoC master/slave ports	Transceivers	PCI Express blocks	Ethernet MACs	Interlaken blocks	HSC blocks	AI Engines	Other	Notes
XCVE2002	Versal AI Edge	2500*	20000*	24*	24*	90*	1	4	0	2	-	-	-	-	-	8 AI-ML	XRAM	not yet in production
XCVE2102	Versal AI Edge	4576	36608	47	47	176	1	4	0	2	-	-	-	-	-	12 AI-ML	XRAM	not yet in production
XCVE2202	Versal AI Edge	13125*	105000*	108*	108*	324*	1	4	1	5	8 GTYP	1 Gen4	1 MRMAC	-	-	24 AI-ML (12×2)	XRAM	software-limitted version of XCVE2302, not yet in production
XCVE2302	Versal AI Edge	18784	150272	155	155	464	1	4	1	5	8 GTYP	1 Gen4	1 MRMAC	-	-	34 AI-ML (17×2)	XRAM	not yet in production
XCVE1752	Versal AI Edge	56064	448512	954	462	1312	3	9	2	21	44 GTY	4 Gen4	2 MRMAC	-	-	304 (38×8)	CPM Gen4	software-limitted version of XCVC1702
XCVE2602	Versal AI Edge	46875*	375000*	476*	224*	984*	3	9	2	21	32 GTYP	4 Gen5	2 MRMAC	-	-	152 AI-ML (38×4)	CPM Gen5, 2×VDE	software-limitted version of XCVC2802, not yet in production
XCVE2802	Versal AI Edge	65088	520704	600	264	1312	3	9	2	21	32 GTYP	4 Gen5	2 MRMAC	-	-	304 AI-ML (38×8)	CPM Gen5, 4×VDE	software-limitted version of XCVC2802, not yet in production
XCVC1352	Versal AI Core	30848	246784	441	209	928	2	7	2	10	8 GTYP	1 Gen4	1 MRMAC	-	-	128	XRAM	not yet in production
XCVC1502	Versal AI Core	46544	372352*	848	390	1032	3	9	1	21	32 GTY	4 Gen4	3 MRMAC	-	-	198 (33×6)	CPM Gen4	software-limitted version of XCVC1702
XCVC1702	Versal AI Core	56064	448512	954	462	1312	3	9	2	21	44 GTY	4 Gen4	4 MRMAC	-	-	304 (38×8)	CPM Gen4
XCVC1802	Versal AI Core	90625*	725000*	800*	325*	1600*	4	12	2	28	44 GTY	4 Gen4	4 MRMAC	-	-	300 (50×6)	CPM Gen4	software-limitted version of XCVC1902
XCVC1902	Versal AI Core	112480	899840	967	463	1968	4	12	2	28	44 GTY	4 Gen4	4 MRMAC	-	-	400 (50×8)	CPM Gen4
XCVC2602	Versal AI Core	46875*	375000*	476*	224*	984*	3	9	2	21	32 GTYP	4 Gen5	2 MRMAC	-	-	152 AI-ML (38×4)	CPM Gen5, 2×VDE	software-limitted version of XCVC2802, not yet in production
XCVC2802	Versal AI Core	65088	520704	600	264	1312	3	9	2	21	32 GTYP	4 Gen5	2 MRMAC	-	-	304 AI-ML (38×8)	CPM Gen5, 4×VDE	not yet in production
XCVM1102	Versal Prime	18784	150272	155	155	464	1	4	1	5	8 GTYP	1 Gen4	1 MRMAC	-	-	-	XRAM	software-limitted version of XCVE2302, not yet in production
XCVM1302	Versal Prime	39616*	316928*	502*	178*	832*	2	8	1	9*	24 GTY	2 Gen4	2 MRMAC	-	-	-	CPM Gen4	software-limitted version of XCVM1402
XCVM1402	Versal Prime	70720	565760	1150	286	1696	4	12	1	18	24 GTY	2 Gen4	2 MRMAC	-	-	-	CPM Gen4
XCVM1502	Versal Prime	56064	448512	954	462	1312	3	9	2	21	44 GTY	4 Gen4	4 MRMAC	-	-	-	CPM Gen4	XCVC1702 with AI Engines disabled
XCVM1802	Versal Prime	112480	899840	967	463	1968	4	12	2	28	44 GTY	4 Gen4	4 MRMAC	-	-	-	CPM Gen4	XCVC1902 with AI Engines disabled
XCVM2202	Versal Prime	65088	520704	600	264	1312	3	9	2	21	32 GTYP	4 Gen5	2 MRMAC	-	-	-	CPM Gen5	XCVC2802 with AI Engines and VDE disabled, not yet in production
XCVM2302	Versal Prime	89984	719872	1405	453	1904	3	9	2	30	8 GTYP + 40 GTM	2 Gen5	6 MRMAC	-	-	-	-	software-limitted version of XCVP1402, not yet in production
XCVM2502	Versal Prime	112528	900224	1341	677	3984	4	12	-	28	16 GTYP	2 Gen5	2 MRMAC	-	-	-	CPM Gen5	software-limitted version of XCVP1202, not yet in production
XCVM2902	Versal Prime	127616	1020928	1981	645	2672	3	9	2	42	8 GTYP + 40 GTM	2 Gen5	6 MRMAC	-	-	-	-	software-limitted version of XCVP1402, not yet in production
XCVP1002	Versal Premium	47600*	380800*	535*	345*	1140*	2	7	-	16*	20 GTY + 24 GTM	1 Gen4	3 MRMAC + 2 DCMAC	1	1	-	CPM Gen4	software-limitted version of XCVP1052, not yet in production
XCVP1052	Versal Premium	67760	542080	751	489	1572	2	7	-	22	20 GTY + 48 GTM	1 Gen4	5 MRMAC + 3 DCMAC	2	1	-	CPM Gen4	not yet in production
XCVP1102	Versal Premium	89984	719872	1405	453	1904	3	9	2	30	8 GTYP + 64 GTM	2 Gen5	6 MRMAC + 4 DCMAC	2	3	-	-	software-limitted version of XCVP1402
XCVP1202	Versal Premium	112528	900224	1341	677	3984	4	13	-	28	28 GTYP + 20 GTM	2 Gen5	2 MRMAC + 1 DCMAC	-	1	-	CPM Gen5
XCVP1402	Versal Premium	127616	1020928	1981	645	2672	3	9	2	42	8 GTYP + 96 GTM	2 Gen5	6 MRMAC + 8 DCMAC	2	5	-	-
XCVP1502	Versal Premium	215056	1720448	2541	1301	7440	4	13	-	52	28 GTYP + 60 GTM	2 Gen5	4 MRMAC + 3 DCMAC	1	2	-	CPM Gen5	multi-die device consisting of XCVP1202 + an extension die
XCVP1552	Versal Premium	219248	1753984	2541	1301	7392	4	13	-	52	68 GTYP + 20 GTM	8 Gen5	4 MRMAC + 1 DCMAC	-	2	-	CPM Gen5	XCVH15x2 without HBM
XCVP1702	Versal Premium	317584	2540672	3741	1925	10896	4	13	-	76	28 GTYP + 100 GTM	2 Gen5	6 MRMAC + 5 DCMAC	2	3	-	CPM Gen5	multi-die device consisting of XCVP1202 + 2× extension die (same as XCVP1502)
XCVP1802	Versal Premium	420112	3360896	4941	2549	14352	4	13	-	100	28 GTYP + 140 GTM	2 Gen5	8 MRMAC + 7 DCMAC	3	4	-	CPM Gen5	multi-die device consisting of XCVP1202 + 3× extension die (same as XCVP1502)
XCVP2502	Versal Premium	213584	1708672	2541	1301	7392	4	13	-	52	28 GTYP + 60 GTM	2 Gen5	4 MRMAC + 3 DCMAC	1	2	472 (59×8)	CPM Gen5	multi-die device consisting of XCVP1202 + AI extension die
XCVP2802	Versal Premium	418640	3349120	4941	2549	14304	4	13	-	100	28 GTYP + 140 GTM	2 Gen5	8 MRMAC + 7 DCMAC	3	4	472 (59×8)	CPM Gen5	multi-die device consisting of XCVP1202 + 2× extension die (same as XCVP1502) + AI extension die (same as XCVP2502)
XCVH1522	Versal HBM	219248	1753984	2541	1301	7392	4	13	-	52	68 GTYP + 20 GTM	8 Gen5	4 MRMAC + 1 DCMAC	-	2	-	CPM Gen5, 8GB HBM	multi-die device consisting of XCVP1202 + HBM extension die + HBM memory stacks, not yet in production
XCVH1542																	CPM Gen5, 16GB HBM
XCVH1582																	CPM Gen5, 32GB HBM
XCVH1742	Versal HBM	321776	2574208	3741	1925	10848	4	13	-	76	68 GTYP + 60 GTM	2 Gen5	6 MRMAC + 3 DCMAC	1	3	-	CPM Gen5, 16GB HBM	multi-die device consisting of XCVP1202 + extension die (same as XCVP1502) + HBM extension die (same as XCVH15x2) + HBM memory stacks, not yet in production
XCVH1782																	CPM Gen5, 32GB HBM

Alveo and Kria

In addition to standalone FPGA chips, Xilinx also offers the Alveo product line of ready-to-use FPGA-based accelerator boards, and the Kria product line of FPGA-based Systems-on-Module (SOMs). The FPGAs used on these boards reuse the same die as standalone chips, but are considered to be distinct products by the Vivado toolchain.

Product	Purpose	FPGA	Corresponding standalone FPGA	Board format	Peripherials on board
Alveo SN1000 SmartNIC [80]	Accelerated network interface controller	XCU26	XCVU23P	PCI Express ×16 full height, half length, single slot	PCI Express Gen 3 ×16 or Gen 4 ×8 interface to FPGA Dedicated 16-core ARMv8 Cortex-A72 CPU (NXP Layerscape LX2162A), connected to FPGA via internal PCI Express Gen 3 ×8 link 4GB 72-bit component DDR4 RAM for the ARM CPU 2×4GB 72-bit component DDR4 RAM for the FPGA 2×QSFP28 100 Gigabit Ethernet 16GB of eMMC NAND flash 64MB of NOR flash NC-SI sideband connector
Alveo U25N		XCU25	XCZU19EG	PCI Express ×16 half height, half length, single slot	PCI Express Gen 3 ×16 interface to the FPGA's PS block 2GB 40-bit component DDR4 RAM for the PS block 4GB 72-bit component DDR4 RAM for the FPGA fabric 2×SFP28 25 Gigabit Ethernet XtremeScale X2 Ethernet Controller Propertiary DMB-1 maintenance port for configuration
Alveo U30	Media accelerator card	2×XCU30	2×XCZU7EV	PCI Express ×8 half height, half length, single slot	bifurcated 2× PCI Express Gen 3 ×4 interface to the FPGAs' PS blocks (×4 lanes per device) 2×4GB 72-bit component DDR4 RAM Configuration flash Propertiary maintenance port for configuration
Alveo U55C [81]	High performance compute card	XCU55C	XCVU47P	PCI Express ×16 full height, half length, single slot	PCI Express Gen 3 ×16 or Gen 4 ×8 interface to FPGA 16GB of HBM2 RAM (on FPGA) 2×QSFP28 100 Gigabit Ethernet Configuration flash TI MSP432 satellite controller Micro USB port for configuration Propertiary DMB-1 maintenance port for configuration
Alveo U50 [82]	Data center accelerator card	XCU50	XCVU35P	PCI Express ×16 half height, half length, single slot	PCI Express Gen 3 ×16 or Gen 4 ×8 interface to FPGA 8GB of HBM2 RAM (on FPGA) QSFP28 100 Gigabit Ethernet Configuration flash TI MSP432 satellite controller Propertiary DMB-1 maintenance port for configuration
Alveo U200 [83]		XCU200	XCVU9P	PCI Express ×16 full height, full or ¾ length, dual slot	PCI Express Gen 3 ×16 interface to FPGA 4× DDR4 DIMM sockets with 4× 16GB RAM preinstalled 2×QSFP28 100 Gigabit Ethernet Configuration flash TI MSP432 satellite controller Micro USB port for configuration
Alveo U250		XCU250	XCVU13P
Alveo U280 [84]		XCU280	XCVU37P		PCI Express Gen 3 ×16 or Gen 4 ×8 interface to FPGA 8GB of HBM2 RAM (on FPGA) 2× DDR4 DIMM sockets with 2× 16GB RAM preinstalled 2×QSFP28 100 Gigabit Ethernet Configuration flash Satellite controller Micro USB port for configuration
Alveo X3522 [85]	Low Latency Network Adapter	XCUX35	XCVU23P	PCI Express ×8 half height, half length, single slot	PCI Express Gen 3 ×8 or Gen 4 ×8 interface to FPGA 2×4GB 72-bit component DDR4 RAM 2×DSFP28 50 Gigabit Ethernet Configuration flash LPC5500 satellite controller Propertiary maintenance port for configuration
Alveo X3522PV	Adaptable Accelerator Card
Kria K26		XCK26	XCZU5EV	System on Module	33.33 MHz oscillator, 32.768 kHz RTC crystal 4GB 64-bit component DDR4 RAM (for PS block) 16GB eMMC flash 64MB QSPI flash 8kB I2C EEPROM TPM 2.0 Power supply circuit, powered by a single 5V input Two custom power+IO connectors, exposing HPIO, HDIO, GTH, and GTR pins of the FPGA

FPGAs without integrated CPUs ^[86]

Artix

Family	Launch	Process	Logic cells			Block RAM		DSP slices			MGT				PCIe blocks		Mem Intf BW		IO pins	VCCINT
		nm	Count (K)	TITO (ns)	TCKO (ns)	Total (Mb)	FMAX (MHz)	Count	Total GMAC/s	FMAX (MHz)	Type	Count	Gbps	Total Gbps	Type	Count	Type	Gbps
Artix-7	2010	28 nm	16-215	0.94	0.4	0.9-13	509	45-740	929	628	GTP	0-16	6.6	211	x4 Gen2	1	DDR3	1066	106-500	1.00

Kintex

Family	Launch	Process	Logic cells			Block RAM		UltraRAM		DSP slices			MGT				PCIe blocks		Mem Intf BW		IO pins	VCCINT
		nm	Count (K)	TITO (ns)	TCKO (ns)	Total (Mb)	FMAX (MHz)	Total (Mb)	FMAX (MHz)	Count	Total GMAC/s	FMAX (MHz)	Type	Count	Gbps	Total Gbps	Type	Count	Type	Gbps
Kintex-7	2010	28 nm	66-478	0.58	0.26	5-34	601			240-1920	2845	741	GTX	4-32	12.5	800	x8 Gen2	1	DDR3	1866	285-500	1.00
Kintex UltraScale	2013 [87]	20 nm	318-1451			12.7-75.9	660			768-5520	8180	741	GTH, GTY	12-64	16.3	2086	x8 Gen3	1-6	DDR3	2400	312-832	0.95
Kintex UltraScale+	2015 [88]	16 nm	356-1143			12.7-34.6	825	0-36	650	1368-3528	6287	891	GTH, GTY	16-76	32.75	3268	x16 Gen3	0-5	DDR4	2666	280-668	0.85

See also

• List of Lattice FPGAs

References

1. Akthar, Shahul (2014-09-21). "Block RAM and Distributed RAM in Xilinx FPGA". All About FPGA. Retrieved 2018-12-03.
2. "UltraRAM: Breakthrough Embedded Memory Integration on UltraScale+ Devices" (PDF). Xilinx. 2016-06-14. Retrieved 2018-12-03.
3. "Xcell Journal: Issue 10" (PDF).
4. "Logic cell concept in xilinx fpgas". forums.xilinx.com. 2010-02-13. Retrieved 2021-04-26.
5. "Marketing Math 201". EEJournal. 2015-11-24. Retrieved 2021-04-28.
6. "Xcell Journal: Issue 3" (PDF).
7. "Xcell Journal: Issue 9" (PDF).
8. "Xcell Journal: Issue 8" (PDF).
9. "Xcell Journal, Issue 13" (PDF).
10. "Xcell Journal, Issue 19" (PDF).
11. "Xcell Journal, Issue 12" (PDF).
12. "Xcell Journal, Issue 18" (PDF).
13. "XILINX INC (Form Type: 10-K, Filing Date: 06/18/1999". edgar.secdatabase.com. Retrieved 2021-04-24.
14. "XCELL 20 Newsletter (Q1 96)" (PDF).
15. "XILINX INC (Form Type: 10-K, Filing Date: 06/19/1998". edgar.secdatabase.com. Retrieved 2021-04-24.
16. "Xilinx Xcell Journal Issue 30" (PDF).
17. "XILINX INC (Form Type: 10-K, Filing Date: 06/12/2003". edgar.secdatabase.com. Retrieved 2021-04-24.
18. "Xilinx Xcell Quarterly Newsletter #22 (Q3 96)" (PDF).
19. "XILINX INC (Form Type: 10-K, Filing Date: 06/12/2001". edgar.secdatabase.com. Retrieved 2021-04-24.
20. "XILINX INC (Form Type: 10-K, Filing Date: 06/04/2004)". edgar.secdatabase.com. Retrieved 2021-04-24.
21. "XILINX INC (Form Type: 10-K, Filing Date: 06/17/2002)". edgar.secdatabase.com. Retrieved 2021-04-24.
22. "Xcell Journal, Issue 46" (PDF).
23. "XILINX INC (Form Type: 10-K, Filing Date: 06/01/2005)". edgar.secdatabase.com. Retrieved 2021-04-24.
24. "XILINX INC Form 10-K Annual Report Filed 2020-05-08". edgar.secdatabase.com. Retrieved 2021-04-24.
25. Xilinx. "XC2000 Logic Cell Array Families Product Description" (PDF).
26. Xilinx. "XC3000 Logic Cell Array Families" (PDF).
27. Xilinx. "XC4000, XC4000A, XC4000H Logic Cell Array Families" (PDF).
28. Xilinx. "XC4000E and XC4000X Series FPGA data sheet" (PDF).
29. Xilinx. "XC4000XLA/XV Field Programmable Gate Arrays" (PDF).
30. Xilinx. "Spartan and Spartan-XL FPGA Families Data Sheet" (PDF).
31. Xilinx. "XC5200 Series Field Programmable Gate Arrays" (PDF).
32. "Xilinx Programmable Logic Data Book" (PDF).
33. "Spartan-II FPGA Family Data Sheet" (PDF).
34. "Virtex™ 2.5V Field Programmable Gate Arrays" (PDF).
35. "Virtex™-E 1.8V Field Programmable Gate Arrays" (PDF).
36. "Spartan-IIE FPGA Family Data Sheet" (PDF).
37. "Virtex™-E 1.8V Extended Memory Field Programmable Gate Arrays" (PDF).
38. "Virtex-II Platform FPGAs: Complete Data Sheet" (PDF).
39. "Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview" (PDF).
40. "Spartan-3 FPGA Family Data Sheet" (PDF).
41. "Spartan-3E FPGA Family Data Sheet" (PDF).
42. "Spartan-3A FPGA Family: Data Sheet" (PDF).
43. "Spartan-3A DSP FPGA Family Data Sheet" (PDF).
44. "Virtex-4 Family Overview" (PDF).
45. "Virtex-4 FPGA User Guide" (PDF).
46. "XtremeDSP for Virtex-4 FPGAs, User Guide" (PDF).
47. "Virtex-5 Family Overview" (PDF).
48. "Virtex-5 FPGA User Guide" (PDF).
49. "Virtex-5 FPGA XtremeDSP Design Considerations, User Guide" (PDF).
50. "Virtex-5 FPGA RocketIO GTP Transceiver User Guide" (PDF).
51. "Virtex-5 RocketIO GTX Transceiver, User Guide" (PDF).
52. "Virtex-6 Family Overview" (PDF).
53. "Virtex-6 FPGA Configurable Logic Block, User Guide" (PDF).
54. "Virtex-6 FPGA Memory Resources User Guide" (PDF).
55. "Virtex-6 FPGA DSP48E1 Slice, User Guide" (PDF).
56. "Virtex-6 FPGA SelectIO Resources, User Guide" (PDF).
57. "Virtex-6 FPGA Clocking Resources User Guide" (PDF).
58. "Virtex-6 CXT Family Data Sheet" (PDF).
59. "Spartan-6 Family Overview" (PDF).
60. "Spartan-6 FPGA Configurable Logic Block User Guide" (PDF).
61. "Spartan-6 FPGA Block RAM Resources User Guide" (PDF).
62. "Spartan-6 FPGA DSP48A1 Slice" (PDF).
63. "Spartan-6 FPGA SelectIO Resources User Guide" (PDF).
64. "Spartan-6 FPGA Memory Controller User Guide" (PDF).
65. "Spartan-6 FPGA Clocking Resources" (PDF).
66. "Spartan-6 FPGA GTP Transceivers User Guide" (PDF).
67. "7 Series FPGAs Data Sheet: Overview" (PDF).
68. "7 Series FPGAs SelectIO Resources User Guide" (PDF).
69. "7 Series FPGAs Clocking Resources User Guide" (PDF).
70. "7 Series FPGAs GTP Transceivers User Guide" (PDF).
71. "7 Series FPGAs GTX/GTH Transceivers" (PDF).
72. "Zynq-7000 SoC Technical Reference Manual" (PDF).
73. "Zynq-7000 SoC Data Sheet: Overview" (PDF).
74. "Are Xilinx XC7A35T actually the same die as something else or...? - Page 1". www.eevblog.com. Retrieved 2021-04-25.
75. "UltraScale Architecture and Product Data Sheet: Overview" (PDF).
76. "UltraScale Architecture SelectIO Resources User Guide" (PDF).
77. "UltraScale Architecture and Product Data Sheet: Overview" (PDF). Xilinx. Retrieved 2018-12-03.
78. Merritt, Rick (2018-10-03). "Xilinx Unveils Versal SoC". EE Times Asia. Retrieved 2018-12-03.
79. "Versal Architecture and Product Data Sheet: Overview (DS950)" (PDF).
80. "Alveo SN1000 SmartNICs Data Sheet (DS989) (v1.4)". 2022-04-22.
81. "Alveo U55C Data Center Accelerator Cards Data Sheet (DS978) (v1.1)" (PDF). 2022-09-01.
82. "Alveo U50 Data Center Accelerator Card Data Sheet (DS965) (v1.7.1)" (PDF). 2022-08-27.
83. "Alveo U200 and U250 Data Center Accelerator Cards Data Sheet (DS962) (v1.5)". 2022-09-01.
84. "Alveo U280 Data Center Accelerator Card Data Sheet (DS963) (v1.5)". 2022-09-01.
85. "Alveo X3522 Data Sheet (DS1002) (v1.0)". 2022-10-18.
86. Lazzaro, John. "Xilinx Part Family History". UC Berkeley. Retrieved 2018-12-03.
87. "First 20nm UtraScale ASIC-Class FPGA From Xilinx". EE Times. 2013-07-09. Retrieved 2018-12-03.
88. "Xilinx Unveils 16nm Ultrascale+ FPGAs, MPSoCs & 3D ICs". EE Times. 2015-02-24. Retrieved 2018-12-03.