Execute instruction

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In a computer instruction set architecture (ISA), an execute instruction is a machine language instruction which treats data as a machine instruction and executes it.

Contents

It can be considered a fourth mode of instruction sequencing after ordinary sequential execution, branching, and interrupting. [1] Since it is an instruction that operates on other instructions like the repeat instruction, it has also been classified as a meta-instruction. [2]

Computer models

Many computer families introduced in the 1950s and 1960s include execute instructions: the IBM 709 [1] and IBM 7090 (op code mnemonic: XEC), [3] the IBM 7030 Stretch (EX, EXIC), [4] [1] the PDP-1/-4/-7/-9/-15 (XCT), [5] [6] the UNIVAC 1100/2200 (EXRI), [7] the CDC 924 (XEC), [8] the PDP-6/-10 (XCT), the IBM System/360 (EX), [9] the GE-600/Honeywell 6000 (XEC, XED), [10] the SDS-9xx (EXU), [11] the SDS 92 (EXU), [12] and the SDS Sigma series (EXU). [13]

Fewer 1970s designs include execute instructions: the Nuclear Data 812 minicomputer (1971) (XCT), [14] the HP 3000 (1972) (XEQ), [15] and the Texas Instruments TI-990 (1975) [16] and its microprocessor version, the TMS9900 (1976) (X). [17] The Signetics 8X300 (1976) is a rare microprocessor design with an execute instruction. XEC executes one instruction from a table of 1 to 255 instructions. Most instructions act as single instruction subroutines but branches are used to implement jump tables. [18] An execute instruction was proposed for the PDP-11 in 1970, [19] but never implemented for it [20] or its successor, the VAX. [21]

Modern instruction sets do not include execute instructions because they interfere with pipelining, prefetching, and other optimizations.[ citation needed ]

Semantics

The instruction to be executed, the target instruction, may be in a register or fetched from memory. Some architectures allow the target instruction to itself be an execute instruction; others do not.

The target instruction is executed as if it were in the memory location of the execute instruction. If, for example, it is a subroutine call instruction, execution is transferred to the subroutine, with the return location being the location after the execute instruction. However, some architectures implement variants of the execute instruction which inhibit branches. [1]

The System/360 supports variable-length target instructions. It also supports modifying the target instruction before executing it. The target instruction must start on an even-numbered byte. [9]

The GE-600 series supports execution of two-instruction sequences, which must be doubleword-aligned. [10]

Some architectures support an execute instruction which operates in a different protection and address relocation mode. For example, the ITS PDP-10 paging device supports a privileged-mode XCTR 'execute relocated' instruction which allows memory reads, writes, or both to use the user-mode page mappings. [22] Similarly, the KL10 variant of the PDP-10 supports the privileged instruction PXCT 'previous context XCT'. [23]

The execute instruction can cause several problems when one execute instruction points to another one and so on:

Similar issues arise with multilevel indirect addressing modes.

Applications

The execute instruction has several applications: [1]

Notes

  1. 1 2 3 4 5 6 7 8 Brooks, F.P. (March 1960). "The execute operations—a fourth mode of instruction sequencing". Communications of the ACM. 3 (3): 168–170. doi: 10.1145/367149.367168 . S2CID   37725430.
  2. ↑ Rossman, George E. (December 1975). "A Course of Study in Computer Hardware Architecture". IEEE Computer. 8 (12): 44–63. doi:10.1109/C-M.1975.218835. S2CID   977792., p. 50
  3. ↑ Reference Manual, IBM 7090 Data Processing System (PDF). IBM. March 1962. p. 36.
  4. ↑ Reference Manual, 7030 Data Processing System (PDF). IBM. August 1961. p. 50.
  5. ↑ Programmed Data Processor-1 Manual (PDF). Digital Equipment Corporation. 1961. p. 14.
  6. ↑ Supnik, Bob. "Architectural Evolution in DEC's 18b Computers" (PDF). p. 8 (page numbers not shown).
  7. ↑ Univac 1107 Central Computer (PDF). November 1961. p. 12-1.
  8. ↑ Control Data 924 Computer Reference Manual (PDF). October 1962. p. 2-41.
  9. 1 2 IBM System/360 Principles of Operation (PDF). IBM. 1964. p. 65. A22-6821-0.
  10. 1 2 GE-635 System Manual (PDF). General Electric Computer Department. July 1964. p. A-5.
  11. ↑ SDS 940 Theory of Operation (PDF). Scientific Data Systems. March 1967. p. 2-12. SDS-98-01-26A.
  12. ↑ SDS 92 Computer. Scientific Data Systems. June 1965. p. 2-6.
  13. ↑ Xerox SIGMA 7 Computer: Reference Manual (PDF). 90 09 5J; XG46, File No: 1X03 (0 ed.). Xerox Corporation. October 1973. pp. 70–71.{{cite book}}: CS1 maint: others (link)
  14. ↑ Principles of Programming the ND812 Computer (PDF). Nuclear Data, Inc. 1971. p. 4-4.
  15. ↑ HP 3000 Computer System: Machine Instruction Set Reference Manual (PDF). Hewlett-Packard. 1980. p. 2-31.
  16. ↑ 990 Computer Family Systems Handbook (PDF). Texas Instruments. p. 3-28.
  17. ↑ TMS 9900 Microprocessor Data Manual (PDF). Texas Instruments. December 1976. p. 24.
  18. ↑ "SL8X305 Microcontroller" (PDF). Lansdale Semiconductor Inc. Retrieved 20 June 2017.
  19. 1 2 van de Goor, Ad (September 21, 1970). "The Execute Instruction" (PDF). PDP-11/40 Technical Memorandum 18.
  20. 1 2 PDP11 Processor Handbook: PDP11/04/34a/44/60/60 (PDF). Digital Equipment Corporation. 1979.
  21. ↑ VAX MACRO and Instruction Set Reference Manual (PDF). Compaq Computer Corporation. April 2001. AA-PS6GD-TE.
  22. ↑ Holloway, J. (February 20, 1970). "Hardware Memo 2 - PDP-10 Paging Device" (PDF). MIT AI Lab. p. 11.
  23. ↑ DECsystem-10, DECSYSTEM-20 Processor Reference Manual (PDF). Digital Equipment Corporation. June 1982. p. 2-63. AA-H391A-TK, AD-H391A-T1.
  24. ↑ Gabriel, Richard P. (August 1985). Performance and Evaluation of Lisp Systems (PDF). MIT Press. p. 32. ISBN   9780262070935.
  25. ↑ Pitman, Kent M. "PURE". The Revised Maclisp Manual, Sunday Morning Edition.
  26. ↑ Moon, David A. (April 1974). Maclisp Reference Manual (PDF). Revision 0. p. 181.

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