Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining millions or billions of MOS transistors onto a single chip. VLSI began in the 1970s when MOS integrated circuit chips were developed and then widely adopted, enabling complex semiconductor and telecommunication technologies. The microprocessor and memory chips are VLSI devices.
John Kenneth Ousterhout is a professor of computer science at Stanford University. He founded Electric Cloud with John Graham-Cumming. Ousterhout was a professor of computer science at University of California, Berkeley where he created the Tcl scripting language and the Tk platform-independent widget toolkit, and proposed the idea of coscheduling. Ousterhout led the research group that designed the experimental Sprite operating system and the first log-structured file system. Ousterhout also led the team that developed the Magic VLSI computer-aided design (CAD) program.
Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design; this article in particular describes EDA specifically with respect to integrated circuits (ICs).
In integrated circuit design, integrated circuit (IC) layout, also known IC mask layout or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit. Originally the overall process was called tapeout, as historically early ICs used graphical black crepe tape on mylar media for photo imaging.
In geometry, an arrangement of lines is the subdivision of the plane formed by a collection of lines. Problems of counting the features of arrangements have been studied in discrete geometry, and computational geometers have found algorithms for the efficient construction of arrangements.
A silicon compiler is an electronic design automation software tool that is used for high-level synthesis of integrated circuits. Such tool takes a user's specification of an IC design as input and automatically generates an integrated circuit (IC) design files as output for further fabrication by the semiconductor fabrication plant or manually from discrete components. The process is sometimes referred to as hardware compilation. The silicon compiler may use vendor's Process Design Kit for the production.
In electronic design automation, a design rule is a geometric constraint imposed on circuit board, semiconductor device, and integrated circuit (IC) designers to ensure their designs function properly, reliably, and can be produced with acceptable yield. Design rules for production are developed by process engineers based on the capability of their processes to realize design intent. Electronic design automation is used extensively to ensure that designers do not violate design rules; a process called design rule checking (DRC). DRC is a major step during physical verification signoff on the design, which also involves LVS checks, XOR checks, ERC, and antenna checks. The importance of design rules and DRC is greatest for ICs, which have micro- or nano-scale geometries; for advanced processes, some fabs also insist upon the use of more restricted rules to improve yield.
VLSI Technology, Inc., was an American company that designed and manufactured custom and semi-custom integrated circuits (ICs). The company was based in Silicon Valley, with headquarters at 1109 McKay Drive in San Jose. Along with LSI Logic, VLSI Technology defined the leading edge of the application-specific integrated circuit (ASIC) business, which accelerated the push of powerful embedded systems into affordable products.
In geometry, the truncated square tiling is a semiregular tiling by regular polygons of the Euclidean plane with one square and two octagons on each vertex. This is the only edge-to-edge tiling by regular convex polygons which contains an octagon. It has Schläfli symbol of t{4,4}.
In electronic design, wire routing, commonly called simply routing, is a step in the design of printed circuit boards (PCBs) and integrated circuits (ICs). It builds on a preceding step, called placement, which determines the location of each active element of an IC or component on a PCB. After placement, the routing step adds wires needed to properly connect the placed components while obeying all design rules for the IC. Together, the placement and routing steps of IC design are known as place and route.
The VLSI Project was a DARPA-program initiated by Robert Kahn in 1978 that provided research funding to a wide variety of university-based teams in an effort to improve the state of the art in microprocessor design, then known as Very Large Scale Integration (VLSI).
The tetragonal disphenoid tetrahedral honeycomb is a space-filling tessellation in Euclidean 3-space made up of identical tetragonal disphenoidal cells. Cells are face-transitive with 4 identical isosceles triangle faces. John Horton Conway calls it an oblate tetrahedrille or shortened to obtetrahedrille.
The Electric VLSI Design System is an EDA tool written in the early 1980s by Steven M. Rubin. Electric is used to construct logic wire schematics and to perform analysis of integrated circuit layout. It can also handle hardware description languages such as VHDL and Verilog. The system has many analysis and synthesis tools, including design rule checking, simulation, routing, Layout vs. Schematic, logical effort, and more.
ELLA is a hardware description language and support toolset, developed in the United Kingdom by the Royal Signals and Radar Establishment (RSRE) during the 1980s and 1990s, which also developed the compiler for the programming language, ALGOL 68RS, used to write ELLA.
In computational geometry, the largest empty rectangle problem,maximal empty rectangle problem or maximum empty rectangle problem, is the problem of finding a rectangle of maximal size to be placed among obstacles in the plane. There are a number of variants of the problem, depending on the particularities of this generic formulation, in particular, depending on the measure of the "size", domain, and the orientation of the rectangle.
The rectilinear Steiner tree problem, minimum rectilinear Steiner tree problem (MRST), or rectilinear Steiner minimum tree problem (RSMT) is a variant of the geometric Steiner tree problem in the plane, in which the Euclidean distance is replaced with the rectilinear distance. The problem may be formally stated as follows: given n points in the plane, it is required to interconnect them all by a shortest network which consists only of vertical and horizontal line segments. It can be shown that such a network is a tree whose vertices are the input points plus some extra points.
Massoud Pedram is an Iranian American computer engineer noted for his research in green computing, energy storage systems, low-power electronics and design, electronic design automation and quantum computing. In the early 1990s, Pedram pioneered an approach to designing VLSI circuits that considered physical effects during logic synthesis. He named this approach layout-driven logic synthesis, which was subsequently called physical synthesis and incorporated into the standard EDA design flows. Pedram's early work on this subject became a significant prior art reference in a litigation between Synopsys Inc. and Magma Design Automation.
Stephen "Steve" Trimberger is an American computer scientist, electrical engineer, philanthropist, and prolific inventor with 250 US utility patents as of August 26, 2021. He is a DARPA program manager of the microsystems technology office.
Nader Bagherzadeh is a professor of computer engineering in the Department of Electrical Engineering and Computer Science at the University of California, Irvine, where he served as a chair from 1998 to 2003. Bagherzadeh has been involved in research and development in the areas of: Computer Architecture, Reconfigurable Computing, VLSI Chip Design, Network-on-Chip, 3D chips, Sensor Networks, Computer Graphics, Memory and Embedded Systems. Bagherzadeh was named Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2014 for contributions to the design and analysis of coarse-grained reconfigurable processor architectures. Bagherzadeh has published more than 400 articles in peer-reviewed journals and conferences. He was with AT&T Bell Labs from 1980 to 1984.
