TopoR

Last updated

TopoR (Topological Router) [nb 1] is an EDA program developed and maintained by the Russian company Eremex. It is dedicated to laying out a printed circuit board (PCB). The current version is 6.3.17875 as of 2017-09-20. [1]

Contents

It features an autorouter and a set of tools intended to reduce the amount of effort needed for manual routing of a PCB. A distinctive feature of TopoR is the absence of preferred routing directions.

History

Printed circuit board sample Topor board.jpg
Printed circuit board sample

Work on a flexible [2] topological router began in 1988.[ citation needed ]

1996[ citation needed ] saw the release of the first version of a topological router [3] [4] that actually came to be used by industrial enterprises. In 2002, the FreeStyle Router [5] (FSR) by Диал Инжиниринг ("Dial Engineering") ran under DOS and successfully routed dual-layer boards, interfacing with P-CAD. [5] [6] [7] This early router showed the advantages of an innovative approach to routing and high efficiency of the models, algorithms, and software implementation. A 1.44 MB floppy disk was enough for the program and accompanying examples. [5] The company also announced plans to commercially release a FreeStyle Suite for Windows later the year. [8] [7] The last version of FSR for DOS, [9] consisting of the router named SpeedWay and the layout editor named FreeStyle was version 1.6 as of 2003-09-26/2003-11-01. [10] [11] [12]

The first Windows version of the topological router was released in 2001[ citation needed ] and renamed [10] to TopoR. [13] TopoR 1.03 was available on 2003-09-26 and distributed through ElekTrade (ЭлекТрейд). [10] The program routed not only dual-layer but also multi-layer printed circuit boards. [7] TopoR was developed by a group called the FreeStyleTeam, supervised by Sergey J. Luzin (Сергей Юрьевич Лузин), [14] with Oleg B. Polubasov (Олег Борисович Полубасов) as initial FSR developer, as well as Pavel I. Dmitriev (Павел Иванович Дмитриев), Gevorg S. Petrosyan (Геворг Самвелович Петросян), Michael S. Luzin (Михаил Сергеевич Лузин) and Andrew A. Lysenko (Андрей Александрович Лысенко). [15] Version 3.0 was released in 2006. [16] [17] The software was commercially distributed by Prosoft Spb. (ПРОСОФТ СПб) in 2007. [14] TopoR 4.0 added support to import/export DSN design and SES session files. [18] Since TopoR 4.1 (2008) the software is further developed and maintained by Eremex, Ltd.

Features

TopoR can be used as an external autorouter for third-party layout editors or in conjunction with Eremex's own schematic capture and layout editor Delta Design (DD). TopoR imports input in Delta Design's FST format, as Specctra-/ELECTRA-compatible DSN design files, [19] or in P-CAD PCB ASCII (2000, 2002, 2004), PADS PCB ASCII (3.5, 4.0, 5.0, 2005.0), or EAGLE BRD XML formats (6.x). [20] The resulting boards can be exported into Specctra/ELECTRA SES session files, DXF, Gerber, P-CAD PCB ASCII (2000, 2002, 2004), PADS PCB ASCII (3.5, 4.0, 5.0, 2005.0).

Wires consisting of lines only Topor approximation lines.png
Wires consisting of lines only
Wires consisting of lines and arcs Topor approximation arcs.png
Wires consisting of lines and arcs

Routing of the wiring topology is done automatically and flexibly; angles are not limited to 90° and 45°.

Efficient use of PCB space and absence of preferred routing directions in layers considerably reduces electromagnetic crosstalk.[ citation needed ]

TopoR routes all connections, even if this entails violating design constraints. Such violations can be automatically corrected later.

When objects (such as components and vias) are moved around, wire length and shape are optimized automatically with appropriate clearance.

The user is free to choose from two ways to calculate the wire shape: with or without arcs. The first method involves wires consisting of lines only. The other makes wires keep appropriate clearance when circling around pads; it consists of arcs and lines.

TopoR simultaneously optimizes several alternative variants of the layout. Variants with the worst parameters (per total wire length and number of vias) will be removed. [21] [22]

TopoR has an automatic component placement feature. The procedure can be used both for all components of the board and only for components in a specific area. It is not comparable to the quality of the manual placement, but it can be used as a preparation step for manual placement.

The minimum and desired clearances for each net can be specified.

Reduced wire width Topor teardrops.gif
Reduced wire width

TopoR automatically supports trace necking, that is, it reduces the width of a wire that approaches a narrow pad (or one with a diameter that is less than the width of the wire), or when it passes through bottlenecks (for example, between the pads of a component).

Wire-to-pad transitions use teardrop-style smoothing. The use of this procedure at the design stage helps avoid violations in design-rule checking when teardrops are added in the CAM editor.

BGA component routing Topor bga.gif
BGA component routing

TopoR can recognize ball grid array (BGA) component areas and apply a special strategy for routing them. This helps reduce the number of vias, the density of connections, and in some cases the number of routing layers. [23] [24] [25]

Single-layer printed circuit board sample Topor singlelayer.png
Single-layer printed circuit board sample

A special algorithm is used for routing single-layer boards minimizing the number of interlayer junctions or to find a single-layer routing. [26]

Similar solutions

The layout program PCB of the gEDA suite includes a similar topological autorouter named Toporouter, which was written by Anthony Blake in a Google-funded open source project mentored by DJ Delorie in 2008. [27] It is mostly based on an implementation of the algorithms described in Tal Dayan's 1997 PhD thesis, "Rubberband based topological router". [27] [28] This router has meanwhile been adapted for use with the open-source KiCad project as well.

See also

Notes

  1. ↑ In Russian (the mother language of the developers), topor means "axe".

Related Research Articles

<span class="mw-page-title-main">Gerber format</span> Standard file format used for designing printed circuit boards

The Gerber format is an open, ASCII, vector format for printed circuit board (PCB) designs. It is the de facto standard used by PCB industry software to describe the printed circuit board images: copper layers, solder mask, legend, drill data, etc. The standard file extension is .GBR or .gbr though other extensions like .GB, .geb or .gerber are also used.

Schematic capture or schematic entry is a step in the design cycle of electronic design automation (EDA) at which the electronic diagram, or electronic schematic of the designed electronic circuit, is created by a designer. This is done interactively with the help of a schematic capture tool also known as schematic editor.

<span class="mw-page-title-main">EAGLE (program)</span> Scriptable electronic design automation application

EAGLE is a scriptable electronic design automation (EDA) application with schematic capture, printed circuit board (PCB) layout, auto-router and computer-aided manufacturing (CAM) features. EAGLE stands for Easily Applicable Graphical Layout Editor and is developed by CadSoft Computer GmbH. The company was acquired by Autodesk Inc. in 2016 who announced to support the product up to 2026 only.

<span class="mw-page-title-main">TARGET (CAD software)</span>

TARGET 3001! is a CAD computer program for EDA and PCB design, developed by Ing.-Büro Friedrich in Germany. It supports the design of electronic schematics, PCBs, and device front panels. It runs under Windows and is available in English, German and French.

<span class="mw-page-title-main">OrCAD</span> Electronic design automation software

OrCAD Systems Corporation was a software company that made OrCAD, a proprietary software tool suite used primarily for electronic design automation (EDA). The software is used mainly by electronic design engineers and electronic technicians to create electronic schematics, and perform mixed-signal simulation and electronic prints for manufacturing printed circuit boards (PCBs). OrCAD was taken over by Cadence Design Systems in 1999 and was integrated with Cadence Allegro in 2005.

In electronic design, wire routing, commonly called simply routing, is a step in the design of printed circuit boards (PCBs) and integrated circuits (ICs). It builds on a preceding step, called placement, which determines the location of each active element of an IC or component on a PCB. After placement, the routing step adds wires needed to properly connect the placed components while obeying all design rules for the IC. Together, the placement and routing steps of IC design are known as place and route.

<span class="mw-page-title-main">FreePCB</span>

FreePCB is a printed circuit board design program for Microsoft Windows, written by Allan Wright.

<span class="mw-page-title-main">KiCad</span> Free software suite for electronic design automation

KiCad is a free software suite for electronic design automation (EDA). It facilitates the design and simulation of electronic hardware. It features an integrated environment for schematic capture, PCB layout, manufacturing file viewing, ngspice-provided SPICE simulation, and engineering calculation. Tools exist within the package to create bill of materials, artwork, Gerber files, and 3D models of the PCB and its components.

Altium Limited is an American - Australian multinational software company that provides electronic design automation software to engineers who design printed circuit boards. Founded as Protel Systems Pty Ltd in Australia in 1985, the company has regional headquarters in the United States, Australia, China, Europe, and Japan. Its products are designed for use in a Microsoft Windows environment and used in industries such as automotive, aerospace, defense, and telecommunications. Its flagship product, Altium Designer, is a software for unified electronics design.

This page is a comparison of electronic design automation (EDA) software which is used today to design the near totality of electronic devices. Modern electronic devices are too complex to be designed without the help of a computer. Electronic devices may consist of integrated circuits (ICs), printed circuit boards (PCBs), field-programmable gate arrays (FPGAs) or a combination of them. Integrated circuits may consist of a combination of digital and analog circuits. These circuits can contain a combination of transistors, resistors, capacitors or specialized components such as analog neural networks, antennas or fuses.

<span class="mw-page-title-main">Altium Designer</span> Electronic Design Automation Software

Altium Designer (AD) is a PCB and electronic design automation software package for printed circuit boards. It is developed by Australian software company Altium Limited.

<span class="mw-page-title-main">PCB (software)</span>

PCB is a free and open-source software suite for electronic design automation (EDA) - for printed circuit boards (PCB) layout. It uses GTK+ for its GUI widgets.

<span class="mw-page-title-main">DesignSpark PCB</span>

DesignSpark PCB is a free electronic design automation software package for printed circuit boards. Although there is no charge for the software, the user must register with DesignSpark.com to unlock the program and it displays advertisements which must be acknowledged before the user can begin working.

P-CAD was the brand name of Personal CAD Systems, Inc., a California based manufacturer of electronic design automation software. It manufactured a CAD software available for personal computers. The company was divested into ACCEL Technologies which was purchased by Altium in 2000. The last release of the software was in 2006 before it was retired in favor of the Altium Designer product.

<span class="mw-page-title-main">DipTrace</span>

DipTrace is a proprietary software suite for electronic design automation (EDA) used for electronic schematic capture and printed circuit board layouts. DipTrace has four applications: schematic capture editor, PCB layout editor with built-in shape-based autorouter and 3D preview, component editor, and pattern editor.

<span class="mw-page-title-main">Pulsonix</span>

Pulsonix is an electronic design automation (EDA) software suite for schematic capture and PCB design. It is produced by WestDev, which is headquartered in Gloucestershire, England, with additional sales and distribution offices overseas. It was first released in 2001, and runs on Windows.

CircuitMaker is electronic design automation software for printed circuit board designs targeted at the hobby, hacker, and maker community. CircuitMaker is available as freeware, and the hardware designed with it may be used for commercial and non-commercial purposes without limitations. It is currently available publicly as version 2.0 by Altium Limited, with the first non-beta release on January 17, 2016.

<span class="mw-page-title-main">Sergey Sirant</span> Russian badminton player

Sergey Yurevich Sirant is a Russian badminton player. He won his first international title at the 2015 Riga International, and clinched the Grand Prix title in 2017 Russian Open. Sirant was the men's singles National Champions in 2017 and 2018. He competed at the 2020 Tokyo Olympics.

<span class="mw-page-title-main">Fusion 360</span> Computer-aided design (CAD) software application

Fusion 360 is a commercial computer-aided design (CAD), computer-aided manufacturing (CAM), computer-aided engineering (CAE) and printed circuit board (PCB) design software application, developed by Autodesk. It is available for Windows, macOS and web browser, with simplified applications available for Android and iOS. Fusion 360 is licensed as a paid subscription, with a free limited home-based, non-commercial personal edition available.

Specctra is a commercial PCB auto-router originally developed by John F. Cooper and David Chyan of Cooper & Chyan Technology, Inc. (CCT) in 1989. The company and product were taken over by Cadence Design Systems in May 1997. Since its integration into Cadence's Allegro PCB Editor, the name of the router is Allegro PCB Router. The latest version is 17.4 - 22.1.

References

  1. ↑ Обновление версии TopoR 6.3.17875 (in Russian). Eremex. 2017-09-20. Archived from the original on 2017-09-24. Retrieved 2017-09-24.
  2. ↑ Базилевич, Р. П. (1981). Декомпозиционные и топологические методы автоматизированного метода конструирования электронных устройств[Decomposition and topological methods of the automated method of designing electronic devices] (in Russian). Lviv (Львов): Вища школа. p. 168.
  3. ↑ Лузин [Luzin], Юрьевич Сергей [Sergey J.]; Полубасов [Polubasov], Олег Борисович [Oleg B.] (1997). Пакет гибкой трассировки "FreeStyle Route"[A package of flexible routing "FreeStyle Route"] (in Russian). Odessa: Мат-лы междунар. науч.-техн. конф. "Системы и средства передачи и обработки информации" [Mathematical scientific-technical conference "Systems and means of information transmission and processing"]. p. 35.
  4. ↑ Лузин [Luzin], Юрьевич Сергей [Sergey J.]; Полубасов [Polubasov], Олег Борисович [Oleg B.] (1997). Трассировка печатных плат - Новые методы решения старых проблем[Routing of printed circuit boards - New methods for solving old problems]. САПР и графика [CAD and graphics] (in Russian) (11): 58–59.
  5. 1 2 3 Сухарев [Sukharev], А. В. [A. V.] (1999). FreeStyleRoute - Трассировка печатных плат [FreeStyleRoute - PCB routing] (in Russian). St. Petersburg, Russia. Archived from the original on 2017-09-25. Retrieved 2017-09-25.
  6. ↑ Бесплатный трассировщик от "Диал". Computerworld Россия (in Russian). 2002 (8). 2002-03-05. Archived from the original on 2017-09-25. Retrieved 2017-09-25.
  7. 1 2 3 Razevig [Разевиг], Vsevolod [Всеволод] (2002-03-26). Трассировщик FreeStyle Router доступен в Интернете [FreeStyle Router is available on the Internet]. PC Week/RE  / IT week (in Russian). 2002 (11 #329). Archived from the original on 2017-09-25. Retrieved 2017-09-25. […] The company Dial Engineering freely offers on the Internet (www.dial-eng.spb.ru) a gridless PCB router FreeStyle Router for DOS and announced the continuation of the development of a FreeStyle CAD Suite for Windows (the commercial release is planned for 2002). If the DOS version only routes single- and double-layer printed circuit boards, the version for Windows is designed to route multi-layer boards. A distinctive feature of the FreeStyle Router products is a smaller number of vias on the PCB with a smaller total length of conductors; in addition, the optimization of the placement of components is performed during the routing process. The preliminary version of the PCB design can be prepared using CAD-CAD and transferred to FreeStyle Router via PDIF format. The purchase of FreeStyle Router for DOS (price $950) entitles to purchase FreeStyle Suite with 50% discount. […]
  8. ↑ Диал Инжиниринг (2002-02-20). Уникальный трассировщик размещен на сайте [A unique router is available on the site] (in Russian). Archived from the original on 2017-09-26. Retrieved 2017-09-26.
  9. ↑ FreeStyle Router - топологический трассировщик (in Russian). 2003-09-30. Archived from the original on 2017-09-26. Retrieved 2017-09-26.
  10. 1 2 3 "News". ElekTrade. 2003-09-26. Archived from the original on 2003-12-05. […] Today, the developers of the popular domestic autoroute program FreeStyleRoute announced the termination of the further development of its DOS version. In its place will come 32-bit Windows version of the program, called TopoR (TOPOlogical Router). The following changes are made to the version of TopoR 1.03 compared to FSR 1.6 […]
  11. ↑ "Software Download". FreeStyleTeam. 2007. Archived from the original on 2007-11-13. FreeStyleRoute V1.6 Topological PCB router for DOS. Freeware. 1.15 MB (1210820 bytes) 1.6 01.11.2003
  12. ↑ "FreeStyleRoute V1.6 Topological PCB router - Installation Guide". FreeStyleTeam. 2007. Archived from the original on 2007-11-16. The FreeStyleRoute (FSR) program consists of a high-efficiency gridless two-layer PCB router SpeedWay and the FreeStyle editor. The editor can also be applied independently for routed boards corrections. It reaches the quality of routing and placement density, comparable or surpassing high-quality of manual routing. As a result, we have smooth wires, without breaks. The algorithms used in the design, allow to place any number of conductors between components pins. Compatible with P-CAD, by PDF-files. Version for DOS. Freeware. Now the program is not supported.
  13. ↑ Система топологической трассировки печатных плат TopoR ver 1.0 - Руководство пользователя [TopoR 1.0 Topological routing system - User manual](PDF) (in Russian). St. Petersburg, Russia. 2003. Archived from the original (PDF) on 2005-01-16.{{cite book}}: CS1 maint: location missing publisher (link)
  14. 1 2 "Contacts". FreeStyleTeam. Archived from the original on 2007-11-13.
  15. ↑ "About group". FreeStyleTeam. 2007. Archived from the original on 2007-11-13.
  16. ↑ ЭлекТрейд (2006-01-17). Готовится к выходу новая версия трассировщика TopoR 3.0 [Preparing for release a new version of the router TopoR 3.0] (in Russian). Archived from the original on 2017-09-26. Retrieved 2017-09-26.
  17. ↑ "EDA Expert" (PDF). Chip-News (RU) (in Russian). 106 (3): 65–66. 2006. Archived (PDF) from the original on 2017-09-26. Retrieved 2017-09-26.
  18. ↑ "Version History". Eremex, Ltd. 2009. Archived from the original on 2009-03-06.
  19. ↑ Латышев, П. Н. (2011), Каталог САПР 2011—2012 Программы и производители[CAD Catalog 2011-2012 Programs and manufacturers] (in Russian), Moscow: Солон-Пресс, p. 600
  20. ↑ "TopoR Version History - What's New in TopoR version 6.2". Eremex. 2017-09-24. Archived from the original on 2017-09-24. Retrieved 2017-09-24. (NB. Includes a list of new features since TopoR 3.0. TopoR 5.4.14203 (2012-12-21) introduced support for EAGLE: "The Eagle BRD plain-text format is now supported. This format is used by files created in the Eagle 6.0 system.". Improved in TopoR 5.4.14362 (2013-07-02): "During import of Eagle BRD-files: in some cases the angle of rotation of pads was disregarded, in some cases the vias' pad size was assigned incorrectly, sometimes the wires on the inner layers were disappearing.")
  21. ↑ Uvarov [Уваров], A. S. [А. С.] (2006). Проектирование печатных плат: 8 лучших программ[PCB design: The 8 best programs] (in Russian). ДМК Пресс [DMK Press]. ISBN   5-94074-089-8.
  22. ↑ Карабран, В. М.; Зырин, И. Д. (2013). Методы снижения паразитной связи между проводниками[Methods for reducing the parasitic connection between conductors] (in Russian) (3). ТЭМС (TEMS): 68–77.{{cite journal}}: Cite journal requires |journal= (help)
  23. ↑ Лузин [Luzin], Юрьевич Сергей [Sergey J.]; Петросян [Petrosyan], Геворг Самвелович [Gevorg S.]; Полубасов [Polubasov], Олег Борисович [Oleg B.] (2008). Проблемы трассировки печатных плат с BGA-компонентами [Problems of routing PCBs with BGA components](PDF). Chip-News (in Russian). 2008 (5).
  24. ↑ Лузин [Luzin], Юрьевич Сергей [Sergey J.]; Петросян [Petrosyan], Геворг Самвелович [Gevorg S.]; Полубасов [Polubasov], Олег Борисович [Oleg B.] (February 2009). "Probleme beim Routing von Leiterplatten mit BGA-Komponenten". Produktion von Leiterplatten und Systemen (in German). Leuze-Verlag. 2009 (2): 263–270.
  25. ↑ Лузин [Luzin], Юрьевич Сергей [Sergey J.]; Петросян [Petrosyan], Геворг Самвелович [Gevorg S.]; Полубасов [Polubasov], Олег Борисович [Oleg B.] (November 2009). "Problems In Routing of PCB with BGA Components". OnBoard Technology. 2009 (11): 12–15. Archived from the original on 2012-04-26.
  26. ↑ Полубасов [Polubasov], Олег Борисович [Oleg B.] (2001) [2000-10-19]. "Глобальная минимизация количества межслой-ных переходов" [Global minimization of the number of interlayer junctions]. Технология и конструирование в электронной аппаратуре (TKEA) (in Russian). НИИ "Звезда", St. Petersburg, Russia. 2001 (2). УДК 681.14. Archived from the original on 2017-09-24. Retrieved 2017-09-24.
  27. 1 2 Blake, Anthony (2009-07-07) [2008]. "Topological Autorouter - Introduction". Archived from the original on 2011-02-27.
  28. ↑ Dayan, Tal (June 1997). Rubberband based topological router (PDF) (PhD thesis). University of California Santa Cruz. S2CID   107646249. Archived from the original (PDF) on 2017-07-18. Retrieved 2017-09-25– via Semantic Scholar.

Further reading

English
Russian
German
This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.