![]() | This article may be too technical for most readers to understand.(December 2008) |
Computational lithography (also known as computational scaling) is the set of mathematical and algorithmic approaches designed to improve the resolution attainable through photolithography. Computational lithography came to the forefront of photolithography technologies in 2008 when the semiconductor industry faced challenges associated with the transition to a 22 nanometer CMOS microfabrication process and has become instrumental in further shrinking the design nodes and topology of semiconductor transistor manufacturing.
Computational lithography means the use of computers to simulate printing of micro-lithography structures. Pioneering work was done by Chris Mack at NSA in developing PROLITH, Rick Dill at IBM and Andy Neureuther at University of California, Berkeley from the early 1980s. These tools were limited to lithography process optimization as the algorithms were limited to a few square micrometres of resist. Commercial full-chip optical proximity correction (OPC), using model forms, was first implemented by TMA (now a subsidiary of Synopsys) and Numerical Technologies (also part of Synopsys) around 1997. [1]
Since then the market and complexity has grown significantly. With the move to sub-wavelength lithography at the 180 nm and 130 nm nodes, RET techniques such as Assist features, phase shift masks started to be used together with OPC. For the transition from 65 nm to 45 nm nodes customers were worrying that not only that design rules were insufficient to guarantee printing without yield limiting hotspots, but also that tape-out time may need thousands of CPUs or weeks of run time. This predicted exponential increase in computational complexity for mask synthesis on moving to the 45 nm process node spawned a significant venture capital investment in design for manufacturing start-up companies. [2]
A number of startup companies promoting their own disruptive solutions to this problem started to appear, techniques from custom hardware acceleration to radical new algorithms such as inverse lithography were touted to resolve the forthcoming bottlenecks. Despite this activity, incumbent OPC suppliers were able to adapt and keep their major customers, with RET and OPC being used together as for previous nodes, but now on more layers and with larger data files, and turn around time concerns were met by new algorithms and improvements in multi-core commodity processors. The term computational lithography was first used by Brion Technology (now a subsidiary of ASML) in 2005 [3] to promote their hardware accelerated full chip lithography simulation platform. Since then the term has been used by the industry to describe full chip mask synthesis solutions. As 45 nm goes into full production and EUV lithography introduction is delayed, 32 nm and 22 nm are expected to run on existing 193 nm scanners technology.
Now, not only are throughput and capabilities concerns resurfacing, but also new computational lithography techniques such as Source Mask Optimization (SMO) is seen as a way to squeeze better resolution specific to a given design. Today, all the major mask synthesis vendors have settled on the term "computational lithography" to describe and promote the set of mask synthesis technologies required for 22 nm.
Computational lithography makes use of a number of numerical simulations to improve the performance (resolution and contrast) of cutting-edge photomasks. The combined techniques include Resolution Enhancement Technology (RET), Optical Proximity Correction (OPC), Source Mask Optimization (SMO), etc. [4] The techniques vary in terms of their technical feasibility and engineering sensible-ness, resulting in the adoption of some and the continual R&D of others. [5]
Resolution enhancement technologies, first used in the 90 nanometer generation, using the mathematics of diffraction optics to specify multi-layer phase-shift photomasks that use interference patterns in the photomask that enhance resolution on the printed wafer surface.
Optical proximity correction uses computational methods to counteract the effects of diffraction-related blurring and under-exposure by modifying on-mask geometries with means such as: adjusting linewidths depending on the density of surrounding geometries (a trace surrounded by a large open area will be over-exposed compared with the same trace surrounded by a dense pattern), adding "dog-bone" endcaps to the end of lines to prevent line shortening, correcting for electron beam proximity effects
OPC can be broadly divided into rule-based and model-based. [6] Inverse lithography technology, which treats the OPC as an inverse imaging problem, is also a useful technique because it can provide unintuitive mask patterns. [7]
Beyond the models used for RET and OPC, computational lithography attempts to improve chip manufacturability and yields such as by using the signature of the scanner to help improve accuracy of the OPC model: [8] polarization characteristics of the lens pupil, Jones matrix of the stepper lens, optical parameters of the photoresist stack, diffusion through the photoresist, stepper illumination control variables.
Computational effort
The computational effort behind these methods is immense. According to one estimate, the calculations required to adjust OPC geometries to take into account variations to focus and exposure for a state-of-the-art integrated circuit will take approximately 100 CPU-years of computer time. [9] This does not include modeling the 3D polarization of the light source or any of the several other systems that need to be modeled in production computational photolithographic mask making flows. Brion Technologies, a subsidiary of ASML, markets a rack-mounted hardware accelerator dedicated for use in making computational lithographic calculations — a mask-making shop can purchase a large number of their systems to run in parallel. Others have claimed significant acceleration using re-purposed off-the-shelf graphics cards for their high parallel throughput. [10]
The periodic enhancement in the resolution achieved through photolithography has been a driving force behind Moore's Law. Resolution improvements enable printing of smaller geometries on an integrated circuit. The minimum feature size that a projection system typically used in photolithography can print is given approximately by:
where
Historically, resolution enhancements in photolithography have been achieved through the progression of stepper illumination sources to smaller and smaller wavelengths — from "g-line" (436 nm) and "i-line" (365 nm) sources based on mercury lamps, to the current systems based on deep ultraviolet excimer lasers sources at 193 nm. However the progression to yet finer wavelength sources has been stalled by the intractable problems associated with extreme ultraviolet lithography and x-ray lithography, forcing semiconductor manufacturers to extend the current 193 nm optical lithography systems until some form of next-generation lithography proves viable (although 157 nm steppers have also been marketed, they have proven cost-prohibitive at $50M each). [11] Efforts to improve resolution by increasing the numerical aperture have led to the use of immersion lithography. As further improvements in resolution through wavelength reduction or increases in numerical aperture have become either technically challenging or economically unfeasible, much attention has been paid to reducing the k1-factor. The k1 factor can be reduced through process improvements, such as phase-shift photomasks. These techniques have enabled photolithography at the 32 nanometer CMOS process technology node using a wavelength of 193 nm (deep ultraviolet). However, with the ITRS roadmap calling for the 22 nanometer node to be in use by 2011, photolithography researchers have had to develop an additional suite of improvements to make 22 nm technology manufacturable. [12] While the increase in mathematical modeling has been underway for some time, the degree and expense of those calculations has justified the use of a new term to cover the changing landscape: computational lithography.
In integrated circuit manufacturing, photolithography or optical lithography is a general term used for techniques that use light to produce minutely patterned thin films of suitable materials over a substrate, such as a silicon wafer, to protect selected areas of it during subsequent etching, deposition, or implantation operations. Typically, ultraviolet light is used to transfer a geometric design from an optical mask to a light-sensitive chemical (photoresist) coated on the substrate. The photoresist either breaks down or hardens where it is exposed to light. The patterned film is then created by removing the softer parts of the coating with appropriate solvents, also known in this case as developers.
Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design; this article in particular describes EDA specifically with respect to integrated circuits (ICs).
A photomask is an opaque plate with transparent areas that allow light to shine through in a defined pattern. Photomasks are commonly used in photolithography for the production of integrated circuits to produce a pattern on a thin wafer of material. Several masks are used in turn, each one reproducing a layer of the completed design, and together known as a mask set.
Immersion lithography is a photolithography resolution enhancement technique for manufacturing integrated circuits (ICs) that replaces the usual air gap between the final lens and the wafer surface with a liquid medium that has a refractive index greater than one. The resolution is increased by a factor equal to the refractive index of the liquid. Current immersion lithography tools use highly purified water for this liquid, achieving feature sizes below 45 nanometers.
Resolution enhancement technology (RET) is a form of image processing technology used to manipulate dot characteristics popular among laser printer and inkjet printer manufacturers. Closely related RET techniques are also used in VLSI photolithography manufacturing technology, in particular in relation to 90 nanometre technology.
Electron-beam lithography is the practice of scanning a focused beam of electrons to draw custom shapes on a surface covered with an electron-sensitive film called a resist (exposing). The electron beam changes the solubility of the resist, enabling selective removal of either the exposed or non-exposed regions of the resist by immersing it in a solvent (developing). The purpose, as with photolithography, is to create very small structures in the resist that can subsequently be transferred to the substrate material, often by etching.
Masklesslithography (MPL) is a photomask-less photolithography-like technology used to project or focal-spot write the image pattern onto a chemical resist-coated substrate by means of UV radiation or electron beam.
Nanolithography (NL) is a growing field of techniques within nanotechnology dealing with the engineering of nanometer-scale structures on various materials.
Extreme ultraviolet lithography is an optical lithography technology used in semiconductor device fabrication to make integrated circuits (ICs). It uses extreme ultraviolet (EUV) wavelengths near 13.5 nm, using a laser-pulsed tin (Sn) droplet plasma, to produce a pattern by using a reflective photomask to expose a substrate covered by photoresist. It is currently applied only in the most advanced semiconductor device fabrication.
Next-generation lithography or NGL is a term used in integrated circuit manufacturing to describe the lithography technologies in development which are intended to replace current techniques. The term applies to any lithography method which uses a shorter-wavelength light or beam type than the current state of the art, such as X-ray lithography, electron beam lithography, focused ion beam lithography, and nanoimprint lithography. The term may also be used to describe techniques which achieve finer resolution features from an existing light wavelength.
A stepper is a device used in the manufacture of integrated circuits (ICs) that is similar in operation to a slide projector or a photographic enlarger. Stepper is short for step-and-repeat camera. Steppers are an essential part of the complex process, called photolithography, which creates millions of microscopic circuit elements on the surface of silicon wafers out of which chips are made. These chips form the heart of ICs such as computer processors, memory chips, and many other devices.
Nanoimprint lithography (NIL) is a method of fabricating nanometer scale patterns. It is a simple nanolithography process with low cost, high throughput and high resolution. It creates patterns by mechanical deformation of imprint resist and subsequent processes. The imprint resist is typically a monomer or polymer formulation that is cured by heat or UV light during the imprinting. Adhesion between the resist and the template is controlled to allow proper release.
Phase-shift masks are photomasks that take advantage of the interference generated by phase differences to improve image resolution in photolithography. There exist alternating and attenuated phase shift masks. A phase-shift mask relies on the fact that light passing through a transparent media will undergo a phase change as a function of its optical thickness.
Optical proximity correction (OPC) is a photolithography enhancement technique commonly used to compensate for image errors due to diffraction or process effects. The need for OPC is seen mainly in the making of semiconductor devices and is due to the limitations of light to maintain the edge placement integrity of the original design, after processing, into the etched image on the silicon wafer. These projected images appear with irregularities such as line widths that are narrower or wider than designed, these are amenable to compensation by changing the pattern on the photomask used for imaging. Other distortions such as rounded corners are driven by the resolution of the optical imaging tool and are harder to compensate for. Such distortions, if not corrected for, may significantly alter the electrical properties of what was being fabricated. Optical proximity correction corrects these errors by moving edges or adding extra polygons to the pattern written on the photomask. This may be driven by pre-computed look-up tables based on width and spacing between features or by using compact models to dynamically simulate the final pattern and thereby drive the movement of edges, typically broken into sections, to find the best solution,. The objective is to reproduce the original layout drawn by the designer on the semiconductor wafer as well as possible.
Resolution enhancement technologies are methods used to modify the photomasks in the lithographic processes used to make integrated circuits to compensate for limitations in the optical resolution of the projection systems. These processes allow the creation of features well beyond the limit that would normally apply due to the Rayleigh criterion. Modern technologies allow the creation of features on the order of 5 nanometers (nm), far below the normal resolution possible using deep ultraviolet (DUV) light.
Contact lithography, also known as contact printing, is a form of photolithography whereby the image to be printed is obtained by illumination of a photomask in direct contact with a substrate coated with an imaging photoresist layer.
Interference lithography is a technique for patterning regular arrays of fine features, without the use of complex optical systems or photomasks.
Multiple patterning is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence additional exposures would be needed, or else positioning patterns using etched feature sidewalls would be necessary.
Plasmonic nanolithography is a nanolithographic process that utilizes surface plasmon excitations such as surface plasmon polaritons (SPPs) to fabricate nanoscale structures. SPPs, which are surface waves that propagate in between planar dielectric-metal layers in the optical regime, can bypass the diffraction limit on the optical resolution that acts as a bottleneck for conventional photolithography.
In semiconductor device fabrication, the inverse lithography technology (ILT) is an approach to photomask design. This is basically an approach to solve an inverse imaging problem: to calculate the shapes of the openings in a photomask ("source") so that the passing light produces a good approximation of the desired pattern ("target") on the illuminated material, typically a photoresist. As such, it is treated as a mathematical optimization problem of a special kind, because usually an analytical solution does not exist. In conventional approaches known as the optical proximity correction (OPC) a "target" shape is augmented with carefully tuned rectangles to produce a "Manhattan shape" for the "source", as shown in the illustration. The ILT approach generates curvilinear shapes for the "source", which deliver better approximations for the "target".