List of PowerPC processors

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The following is a list of PowerPC processors.

General-purpose PowerPC processors

IBM/Motorola

PowerPC 600 family

  • 601 50 and 66 MHz
  • 602 consumer products (multiplexed data/address bus)
  • 603/603e/603ev notebooks, embedded devices
  • 604/604e/604ev workstations and low end servers
  • 620 the first 64-bit implementation

PowerPC 7xx family

  • 740/750 (1997) 233–366 MHz

Motorola/Freescale

PowerPC 7xx family

PowerPC 74xx family

  • 7400/7410 350–550 MHz, uses AltiVec, a SIMD extension of the original PPC specs
  • 7440/7450 micro-architecture family up to 1.5 GHz and 256 kB on-chip L2 cache and improved Altivec
  • 7447/7457 micro-architecture family up to 1.83 GHz with 512 kB on-chip L2 cache
  • 7448 micro-architecture family (2.0 GHz) in 90 nm with 1MB L2 cache and slightly improved AltiVec (out of order instructions).
  • 8640/8641/8640D/8641D with one or two e600 cores, 1MB L2 cache

IBM

IBM Power microprocessors

  • POWER3, 64-bit, 200–450 MHz (as POWER3-II), originally the PowerPC 630. Introduced in 1998.
  • POWER4, 64-bit, dual core, 1.0–1.9 GHz (as POWER4+), follows the PowerPC 2.00 ISA. Introduced in 2001.
  • POWER5, 64-bit, dual core, 2 way SMT/core, 1.6–2.0 GHz, follows the PowerPC 2.01 ISA. Introduced in 2004.
  • POWER5+, 64-bit, dual core, 2 way SMT/core, 1.9–2.2 GHz, follows the PowerPC 2.02 ISA. Introduced in 2005.
  • POWER6, 64-bit, dual core, 2 way SMT/core, 3.6–4.7 GHz, follows the Power ISA 2.03. Introduced in 2007.
  • POWER6+, 64 bit, dual core, 2 way SMT/core, 5.0 GHz, follows the Power ISA 2.05. Introduced in 2009.
  • POWER7, 64-bit octo core, 4 way SMT/core, 2.4–4.25 GHz, follows the Power ISA 2.06. Introduced in 2010.
  • POWER7+, 64-bit octo core, 4 way SMT/core, 3.0–5.0 GHz, follows the Power ISA 2.06. Introduced in 2012.
  • POWER8, 64-bit, hex or twelve core, 8 way SMT/core, 5.0 GHz, follows the Power ISA 2.07. Introduced in 2014.
  • POWER9, 64-bit, PowerNV 24 cores of 4 way SMT/core, PowerVM 12 cores of 8 way SMT/core, follows the Power ISA 3.0. Introduced in 2016.
  • Power10, 64-bit, 15 SMT8 or 30 SMT4 cores, will follow the Power ISA 3.1. Introduced in 2021.

RS64

  • A10 (Cobra), 50–77 MHz, 1995, single chip processor for Series i
  • A25/30 (Muskie), 125–154 MHz, 1996, multi chip, 4 way SMP for Series i
  • RS64 (Apache), 64-bit, 125 MHz, 1997 for large scale SMP systems Series i and Series p
  • RS64-II (Northstar), 262 MHz, 1998
  • RS64-III (Pulsar, Istar), 450 MHz in 1999, 600 in 2000
  • RS64-IV (Sstar), 750 MHz, multithreading, 2000

PowerPC 7xx family

  • 750CL with 256 kB on die L2 cache at 400–900 MHz introduced in 2006
  • 750CX/CXe with 256 kB on die L2 cache at 350–600 MHz
  • 750FX with 512 kB L2 cache announced by IBM in 2001 and available early 2002 at 1 GHz
  • 750GX with 1 MB L2 cache introduced by IBM in 2003

PowerPC 970 family (known in Apple products as PowerPC G5)

  • 970 (2003), 64-bit, derived from POWER4, enhanced with VMX, 512 kB L2 cache, 1.4–2 GHz
  • 970FX (2004), manufactured at 90 nm, 1.8–2.7 GHz
  • 970GX (2006), manufactured at 90 nm, 1MB L2 cache/core, 1.2–2.5 GHz
  • 970MP (2005), dual core, 1 MB L2 cache/core, 1.6–2.5 GHz

Cell

  • Cell BE, 64-bit PPE-core, 2 way multithreading, VMX, 512 kB L2 cache, 8x SPE, 8x 256 kB Local Store memory, 3.2 GHz, follows the PowerPC 2.02 ISA
  • Cell BE 65 nm, same as above but manufactured on a 65 nm process
  • PowerXCell 8i, same as above but with enhanced double precision SPEs and support for DDR-RAM

Supercomputer

Other

Embedded PowerPC

32-bit and 64-bit PowerPC processors have been a favorite of embedded computer designers. To keep costs low on high-volume competitive products, the CPU core is usually bundled into a system-on-chip (SOC) integrated circuit. SOCs contain the processor core, cache and the processor's local data on-chip, along with clocking, timers, memory (SDRAM), peripheral (network, serial I/O), and bus (PCI, PCI-X, ROM/Flash bus, I2C) controllers. IBM also offers an open bus architecture (called CoreConnect) to facilitate connection of the processor core to memory and peripherals in a SOC design. IBM and Motorola have competed along parallel development lines in overlapping markets. A later development was the Book E PowerPC Specification, implemented by both IBM and Freescale Semiconductor, which defines embedded extensions to the PowerPC programming model.

Contents

AMCC

Broad Reach Engineering

BAE Systems

Culturecom

Cray

Freescale (former Motorola)

IBM (now from AMCC)

Microsoft

Nintendo

P.A. Semi

Rapport

Xilinx

Northbridge

Northbridge or host bridge for PowerPC CPU is an Integrated Circuit (IC) for interfacing PowerPC CPU with memory, and Southbridge IC. Some Northbridge also provide interface for Accelerated Graphics Ports (AGP) bus, Peripheral Component Interconnect (PCI), PCI-X, PCI Express, or Hypertransport bus. Specific Northbridge IC must be used for PowerPC CPU. It is impossible to use Northbridge for Intel or AMD x86 CPU with PowerPC CPU. However it is possible to use certain types of x86 Southbridge in PowerPC based motherboards. Example: VIA 686B and AMD Geode CS5536.

Apple UniNorth 2 AGP used in PowerPC 74xx Based Macs Apple UniNorth 2 AGP (15612007125).jpg
Apple UniNorth 2 AGP used in PowerPC 74xx Based Macs

Apple used their own type of northbridges which were custom ASICs manufactured by VLSI(later Philips),Texas Instruments and Lucent (later agere systems)

List of Northbridge for PowerPC:

See also

References