| General information | |
|---|---|
| Designed by | ARM Holdings |
| Architecture and classification | |
| Instruction set | A64, A32, T32; ARMv9.3-A |
The ARM C-series is a family of ARM architecture processor cores developed by Arm Holdings, introduced in 2025 as part of the Armv9.3 architecture. [1] Designed for consumer and mobile devices, the C-series succeeds ARM's Cortex-A and Cortex-X naming scheme, continuing the company's application processor lineage with updated branding.
All C-series cores are currently 64-bit processors implementing the ARMv9.3-A architecture and feature integrated Scalable Matrix Extension 2 (SME2) technology for accelerated AI workloads. The family emphasizes on-device artificial intelligence capabilities alongside traditional application processing performance.
| 64-bit C-series | ||||
|---|---|---|---|---|
| Year | Small | Medium | Large | Flagship |
| 2025 | C1-Nano | C1-Pro | C1-Premium | C1-Ultra |
The C-series family currently includes four performance tiers: Nano, Pro, Premium and Ultra. Nano are in-order designs, the other three tiers provide out-of-order execution. Each tier targets different performance, energy and area efficiency requirements.
The C1-series was introduced in September 2025 and is the first CPU family built on the Armv9.3 architecture. This architecture includes native support for SME2, providing hardware acceleration for matrix operations commonly used in AI and machine learning workloads.: [2]
SME2 is directly integrated into all C-series CPUs through the Armv9.3 architecture. This extension accelerates matrix-heavy operations used in large language models, media processing, speech recognition, computer vision, and multimodal applications.
The C1-DSU serves as the interconnect and shared cache infrastructure for C-series CPU clusters. It supports the latest architectural features and includes low-power optimizations, enabling improved bandwidth scaling and power efficiency compared to previous-generation DSU implementations.
| Specification | C1-Nano | C1-Pro | C1-Premium | C1-Ultra |
|---|---|---|---|---|
| Architecture & Extensions | ||||
| Architecture | Armv9.3-A (with some Armv9.4 features) | |||
| ISA | AArch64 | |||
| Extensions | SVE2, SME2 (optional), MTE, Cryptography, RAS | SVE2, SME2, MTE, Cryptography, RAS | ||
| Microarchitecture | ||||
| Pipeline Type | In-order | Out-of-Order | ||
| Superscalar | Yes | |||
| Pipeline Features | Decoupled predict/fetch, improved branch prediction, upgraded vector forwarding | Improved branch prediction, enhanced memory subsystem | Streamlined microarchitecture, thermal-aware performance scaling | Expanded caches, advanced prefetching, low-latency pipelines |
| Performance Characteristics | ||||
| Core Type | High-efficiency small | Sustained performance big/mid | Sub-flagship | Flagship |
| Performance Focus | Power reduction, instruction flow efficiency | Sustained workloads, gaming | Area-optimized premium performance | Best-in-class IPC, peak single-thread |
| Cluster Configuration | ||||
| Max CPUs in Cluster | Up to 14 | |||
| Typical Cluster Role | Background processing, always-on AI | Mid/big core in heterogeneous clusters | Sub-flagship in premium SoCs | Primary performance core |
| Physical Addressing | 40-bit | |||
| Memory Hierarchy | ||||
| L1 I-Cache | 32KB or 64KB | 64KB | ||
| L1 D-Cache | 64KB | 128KB | ||
| L2 Cache | Optional, 128KB, 256KB, 384KB, 512KB | 128KB, 256KB, 512KB, 1MB | Up to 1MB | Up to 3MB |
| L3 Cache | Optional, 256KB to 32MB, Shared via DSU | |||
| ECC Support | Yes | |||
| Design Flexibility | ||||
| Area-Optimized Configuration | Yes, by design | Yes, optional | Yes, by default | Yes, optional |
| Power Optimization Features | Idle clock gating during low-IPC execution | — | Dynamic task distribution, thermal-aware scaling | — |
| Target Use Cases | ||||
| Primary Applications | Wearables, always-on AI, background tasks, voice activation | Gaming, video processing, multitasking, mid-tier flagships | Premium smartphones, sub-flagship SoCs | Flagship smartphones, laptops, peak performance workloads |
The C-series CPUs are designed as part of the ARM Lumex compute subsystem (CSS) platform, which provides a complete reference design for mobile and consumer devices. [7] The platform approach allows chip manufacturers to integrate C-series cores with other ARM intellectual property and customize configurations to meet specific product requirements. Different combinations of C-series cores can be deployed across various device tiers. [8] [9]
Like other ARM processor designs, C-series cores are not manufactured or sold directly by ARM Holdings. Instead, ARM licenses synthesizable hardware descriptions and development tools to semiconductor companies, which integrate the cores into custom system-on-chip (SoC) designs. This licensing model allows manufacturers to optimize the implementation for specific process nodes, power targets, and feature sets.
