ARM Cortex-A78

Last updated
ARM Cortex-A78
General information
Launched2020
Designed by ARM Ltd.
Performance
Max. CPU clock rate 2.4 GHz to 3.0 GHz in phones and 3.3 GHz in tablets/laptops 
Cache
L1 cache 32–64 KB (parity)

32kb L1 Instruction cache and 32kb L1 Data cache. or

64kb L1 Instruction cache and 64kb L1 Data cache.

Contents

L2 cache256–512 (private L2 ECC) KiB
L3 cacheOptional, 512 KB to 4 MB (up to 8 MB) with Cortex-X1
Architecture and classification
Microarchitecture ARM Cortex-A78
Instruction set ARMv8-A
Extensions
Physical specifications
Cores
  • 1–4 per cluster
Products, models, variants
Product code name
  • Hercules
Variant
History
Predecessor ARM Cortex-A77
Successor ARM Cortex-A710

The ARM Cortex-A78 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Ltd.'s Austin centre. [1]

Design

The ARM Cortex-A78 is the successor to the ARM Cortex-A77. It can be paired with the ARM Cortex-X1 and/or ARM Cortex-A55 CPUs in a DynamIQ configuration to deliver both performance and efficiency. The processor also claims as much as 50% energy savings over its predecessor. [2]

The Cortex-A78 is a 4-wide decode out-of-order superscalar design with a 1.5K macro-OP (MOPs) cache. It can fetch 4 instructions and 6 Mops per cycle, and rename and dispatch 6 Mops, and 12 μops per cycle. The out-of-order window size is 160 entries and the backend has 13 execution ports with a pipeline depth of 14 stages, and the execution latencies consist of 10 stages. [2] [3] [4]

The processor is built on a standard Cortex-A roadmap and offers a 2.1 GHz (5 nm) chipset which makes it better than its predecessor in the following ways:

There is also extended scalability with extra support from Dynamic Shared Unit for DynamIQ on the chipset. A smaller 32 KB L1 cache from the 64 KB L1 cache configuration is optional. To offset this smaller L1 memory, the branch predictor is better at covering irregular search patterns and is capable of following two taken branches per cycle, which results in fewer L1 cache misses and helps hide pipeline bubbles to keep the core well supplied. The pipeline is one cycle longer compared to the A77, which ensures that the A78 hits a clock frequency target of around 3 GHz. The A78 is a 6 instruction per cycle design.

ARM also introduced a second integer multiply unit in the execution unit and an additional load Address Generation Unit (AGU) to increase both the data load and bandwidth by 50%. Other optimizations of the chipset include fused instructions [5] and efficiency improvements to instruction schedulers, register renaming structures, and the re-order buffer.

L2 cache is available up to 512 KB and has double the bandwidth to maximize the performance, while the shared L3 cache is available up to 4 MB, double that of previous generations. A Dynamic Shared Unit (DSU) also allows for an 8 MB configuration with the ARM Cortex-X1. [3] [4] [2] [6]

Licensing

The Cortex-A78 is available as a SIP core to licensees whilst its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).[ citation needed ]

Usage

The Cortex-A78 was first used in Samsung Exynos 2100 SoC, introduced in November and December 2020 respectively. [7] [8] The custom Kryo 680 Gold core used in the Snapdragon 888 SoC is based on the Cortex-A78 microarchitecture. [9] [10] The Cortex-A78 is also used in the MediaTek Dimensity 1200 and 8000 series. The device is also used in NVIDIA DPU, and in the HiSilicon Kirin 9000s, released in August 2023.

See also

Related Research Articles

<span class="mw-page-title-main">Exynos</span> Family of ARM based system-on-a-chips made by Samsung

The Samsung Exynos, formerly Hummingbird (Korean: 엑시노스), is a series of ARM-based system-on-chips developed by Samsung Electronics' System LSI division and manufactured by Samsung Foundry. It is a continuation of Samsung's earlier S3C, S5L and S5P line of SoCs.

The ARM Cortex-A57 is a central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A57 is an out-of-order superscalar pipeline. It is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores into one die constituting a system on a chip (SoC).

<span class="mw-page-title-main">ARM Cortex-A53</span> Microarchitecture implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings

The ARM Cortex-A53 is one of the first two central processing units implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre, along with the Cortex-A57. The Cortex-A53 is a 2-wide decode superscalar processor, capable of dual-issuing some instructions. It was announced October 30, 2012 and is marketed by ARM as either a stand-alone, more energy-efficient alternative to the more powerful Cortex-A57 microarchitecture, or to be used alongside a more powerful microarchitecture in a big.LITTLE configuration. It is available as an IP core to licensees, like other ARM intellectual property and processor designs.

This is a comparison of ARM instruction set architecture application processor cores designed by ARM Holdings and 3rd parties. It does not include ARM Cortex-R, ARM Cortex-M, or legacy ARM cores.

The ARM Cortex-A72 is a central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Austin design centre. The Cortex-A72 is a 3-way decode out-of-order superscalar pipeline. It is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores into one die constituting a system on a chip (SoC). The Cortex-A72 was announced in 2015 to serve as the successor of the Cortex-A57, and was designed to use 20% less power or offer 90% greater performance.

Qualcomm Kryo is a series of custom or semi-custom ARM-based CPUs included in the Snapdragon line of SoCs.

The ARM Cortex-A73 is a central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Sophia design centre. The Cortex-A73 is a 2-wide decode out-of-order superscalar pipeline. The Cortex-A73 serves as the successor of the Cortex-A72, designed to offer 30% greater performance or 30% increased power efficiency.

The ARM Cortex-A55 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre. The Cortex-A55 is a 2-wide decode in-order superscalar pipeline.

The ARM Cortex-A75 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings's Sophia design centre. The Cortex-A75 is a 3-wide decode out-of-order superscalar pipeline. The Cortex-A75 serves as the successor of the Cortex-A73, designed to improve performance by 20% over the A73 in mobile applications while maintaining the same efficiency.

The ARM Cortex-A76 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre. ARM states a 25% and 35% increase in integer and floating point performance, respectively, over a Cortex-A75 of the previous generation.

The ARM Cortex-A77 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre. ARM announced an increase of 23% and 35% in integer and floating point performance, respectively. Memory bandwidth increased 15% relative to the A76.

The ARM Cortex-X1 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre as part of ARM's Cortex-X Custom (CXC) program.

The ARM Cortex-A710 is the successor to the ARM Cortex-A78, being the First-Generation Armv9 “big” Cortex CPU. It is the companion to the ARM Cortex-A510 "LITTLE" efficiency core. It was designed by ARM Ltd.'s Austin centre. It is the fourth and last iteration of Arm’s Austin core family. It forms part of Arm's Total Compute Solutions 2021 (TCS21) along with Arm's Cortex-X2, Cortex-A510, Mali-G710 and CoreLink CI-700/NI-700.

The ARM Cortex-A510 is the successor to the ARM Cortex-A55 and the first ARMv9 high efficiency "LITTLE" CPU. It is the companion to the ARM Cortex-A710 "big" core. It is a clean-sheet 64-bit CPU designed by ARM Holdings' Cambridge design team.

The ARM Cortex-X2 is a central processing unit implementing the ARMv9-A 64-bit instruction set designed by ARM Holdings' Austin design centre as part of ARM's Cortex-X Custom (CXC) program. It forms part of Arm's Total Compute Solutions 2021 (TCS21) along with Arm's Cortex-A710, Cortex-A510, Mali-G710 and CoreLink CI-700/NI-700.

The ARM Neoverse is a group of 64-bit ARM processor cores licensed by Arm Holdings. The cores are intended for datacenter, edge computing, and high-performance computing use. The group consists of ARM Neoverse V-Series, ARM Neoverse N-Series, and ARM Neoverse E-Series.

The ARM Cortex-X4 is a high-performance CPU core from Arm, released in 2023 as part of Arm's "total compute solution." It serves as the successor of ARM Cortex-X3. X-series CPU cores generally focus on high performance, and can be grouped with other ARM cores, such as ARM Cortex-A720 or/and ARM Cortex-A520 in a System-on-Chip (SoC).

The ARM Cortex-A720 is a CPU core model from Arm unveiled in TCS23, it serves as a successor of the CPU core ARM Cortex-A715, Cortex-A700 CPU cores series generally focus on high performance and efficiency, the CPU core can be paired with other cores in its family like ARM Cortex-X4 or/and ARM Cortex-A520 in a CPU cluster. It can be used as either "big" or "LITTLE".

References

  1. ↑ "Cortex-A78". Arm Developer. Retrieved 2020-07-01.
  2. 1 2 3 Triggs, Robert (2020-05-26). "Arm Cortex-X1 and Cortex-A78 CPUs: Big cores with big differences". Android Authority. Retrieved 2020-06-15.
  3. 1 2 Frumusanu, Andrei. "Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence". www.anandtech.com. Retrieved 2020-06-17.
  4. 1 2 "Arm Unveils the Cortex-A78: When Less Is More". WikiChip Fuse. 2020-05-26. Retrieved 2020-06-17.
  5. ↑ "Macro-Operation Fusion (MOP Fusion) - WikiChip".
  6. ↑ "ARM's Cortex-A78 CPU and Mali-G78 GPU will power 2021's best Android phones". www.theverge.com. 26 May 2020. Retrieved 2020-06-15.
  7. ↑ Frumusanu, Andrei. "Samsung Announces Exynos 1080 - 5nm Premium-Range SoC with A78 Cores". www.anandtech.com. Retrieved 2020-11-13.
  8. ↑ "Exynos 1080 5G Mobile Processor: Specs, Features | Samsung Exynos". Samsung Semiconductor. Retrieved 2021-01-11.
  9. ↑ Frumusanu, Andrei. "Qualcomm Details The Snapdragon 888: 3rd Gen 5G & Cortex-X1 on 5nm". www.anandtech.com. Retrieved 2021-01-11.
  10. ↑ "Everything you need to know about the Qualcomm Snapdragon 888". xda-developers. 2020-12-02. Retrieved 2021-01-11.
This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.