List of ARM processors

Last updated

This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design. [1] Keil also provides a somewhat newer summary of vendors of ARM based processors. [2] ARM further provides a chart [3] displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM core families.

Contents

Processors

Designed by ARM

Product familyARM architectureProcessorFeature Cache (I / D), MMU Typical MIPS @ MHz Reference
ARM1ARMv1ARM1First implementationNone
ARM2ARMv2ARM2ARMv2 added the MUL (multiply) instructionNone0.33 DMIPS/MHz
ARM2aSARMv2aARM250Integrated MEMC (MMU), graphics and I/O processor. ARMv2a added the SWP and SWPB (swap) instructionsNone, MEMC1a
ARM3First integrated memory cache4  KB unified0.50 DMIPS/MHz
ARM6ARMv3ARM60ARMv3 first to support 32-bit memory address space (previously 26-bit).
ARMv3M first added long multiply instructions (32x32=64).		None10 MIPS @ 12 MHz
ARM600As ARM60, cache and coprocessor bus (for FPA10 floating-point unit)4 KB unified28 MIPS @ 33 MHz
ARM610As ARM60, cache, no coprocessor bus4 KB unified17 MIPS @ 20 MHz
0.65 DMIPS/MHz		 [4]
ARM7 ARMv3ARM700coprocessor bus (for FPA11 floating-point unit)8 KB unified40 MHz
ARM710As ARM700, no coprocessor bus8 KB unified40 MHz [5]
ARM710aAs ARM710, also used as core of ARM71008 KB unified40 MHz
0.68 DMIPS/MHz
ARM7T ARMv4T ARM7TDMI(-S)3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bit addressing None15 MIPS @ 16.8 MHz
63 DMIPS @ 70 MHz
ARM710TAs ARM7TDMI, cache8 KB unified, MMU36 MIPS @ 40 MHz
ARM720TAs ARM7TDMI, cache8 KB unified, MMU with FCSE (Fast Context Switch Extension)60 MIPS @ 59.8 MHz
ARM740TAs ARM7TDMI, cache MPU
ARM7EJ ARMv5TEJARM7EJ-S5-stage pipeline, Thumb, Jazelle DBX, enhanced DSP instructionsNone
ARM8ARMv4ARM8105-stage pipeline, static branch prediction, double-bandwidth memory8 KB unified, MMU84 MIPS @ 72 MHz
1.16 DMIPS/MHz		 [6] [7]
ARM9T ARMv4T ARM9TDMI 5-stage pipeline, ThumbNone
ARM920T As ARM9TDMI, cache16 KB / 16 KB, MMU with FCSE (Fast Context Switch Extension)200 MIPS @ 180 MHz [8]
ARM922T As ARM9TDMI, caches8 KB / 8 KB, MMU
ARM940T As ARM9TDMI, caches4 KB / 4 KB, MPU
ARM9E ARMv5TE ARM946E-S Thumb, enhanced DSP instructions, cachesVariable, tightly coupled memories, MPU
ARM966E-S Thumb, enhanced DSP instructionsNo cache, TCMs
ARM968E-S As ARM966E-SNo cache, TCMs
ARMv5TEJ ARM926EJ-S Thumb, Jazelle DBX, enhanced DSP instructionsVariable, TCMs, MMU220 MIPS @ 200 MHz
ARMv5TE ARM996HS Clockless processor, as ARM966E-SNo caches, TCMs, MPU
ARM10EARMv5TEARM1020E6-stage pipeline, Thumb, enhanced DSP instructions, (VFP)32 KB / 32 KB, MMU
ARM1022EAs ARM1020E16 KB / 16 KB, MMU
ARMv5TEJARM1026EJ-SThumb, Jazelle DBX, enhanced DSP instructions, (VFP)Variable, MMU or MPU
ARM11 ARMv6ARM1136J(F)-S8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), enhanced DSP instructions, unaligned memory access Variable, MMU740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz [9]
ARMv6T2ARM1156T2(F)-S9-stage pipeline, SIMD, Thumb-2, (VFP), enhanced DSP instructionsVariable, MPU [10]
ARMv6ZARM1176JZ(F)-SAs ARM1136EJ(F)-SVariable, MMU + TrustZone 965 DMIPS @ 772 MHz, up to 2,600 DMIPS with four processors [11]
ARMv6KARM11MPCoreAs ARM1136EJ(F)-S, 1–4 core SMPVariable, MMU
SecurCoreARMv6-MSC000As Cortex-M00.9 DMIPS/MHz
ARMv4TSC100As ARM7TDMI
ARMv7-MSC300As Cortex-M31.25 DMIPS/MHz
Cortex-M ARMv6-M Cortex-M0 Microcontroller profile, most Thumb + some Thumb-2, [12] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryOptional cache, no TCM, no MPU0.84 DMIPS/MHz [13]
Cortex-M0+ Microcontroller profile, most Thumb + some Thumb-2, [12] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions0.93 DMIPS/MHz [14]
Cortex-M1 Microcontroller profile, most Thumb + some Thumb-2, [12] hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memoryOptional cache, 0–1024 KB I-TCM, 0–1024 KB D-TCM, no MPU136 DMIPS @ 170 MHz, [15] (0.8 DMIPS/MHz FPGA-dependent) [16] [17]
ARMv7-M Cortex-M3 Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions1.25 DMIPS/MHz [18]
ARMv7E-M Cortex-M4 Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv4-SP single-precision FPU, hardware multiply and divide instructions, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions1.25 DMIPS/MHz (1.27 w/FPU) [19]
Cortex-M7 Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv5 single and double precision FPU, hardware multiply and divide instructions0−64 KB I-cache, 0−64 KB D-cache, 0–16 MB I-TCM, 0–16 MB D-TCM (all these w/optional ECC), optional MPU with 8 or 16 regions2.14 DMIPS/MHz [20]
ARMv8-M Baseline Cortex-M23 Microcontroller profile, Thumb-1 (most), Thumb-2 (some), Divide, TrustZoneOptional cache, no TCM, optional MPU with 16 regions1.03 DMIPS/MHz [21]
ARMv8-M Mainline Cortex-M33 Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processorOptional cache, no TCM, optional MPU with 16 regions1.50 DMIPS/MHz [22]
Cortex-M35P Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processorBuilt-in cache (with option 2–16 KB), I-cache, no TCM, optional MPU with 16 regions1.50 DMIPS/MHz [23]
ARMv8.1-M Mainline Cortex-M52 1.60 DMIPS/MHz [24]
Cortex-M55 1.69 DMIPS/MHz [25]
Cortex-M85 3.13 DMIPS/MHz [26]
Cortex-R ARMv7-R Cortex-R4 Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic0–64 KB / 0–64 KB, 0–2 of 0–8  MB TCM, opt. MPU with 8/12 regions1.67 DMIPS/MHz [27] [28]
Cortex-R5 Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP) [29] 0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 12/16 regions1.67 DMIPS/MHz [27] [30]
Cortex-R7 Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP [29] 0–64 KB / 0–64 KB, ? of 0–128 KB TCM, opt. MPU with 16 regions2.50 DMIPS/MHz [27] [31]
Cortex-R8 TBD0–64 KB / 0–64 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24 regions2.50 DMIPS/MHz [27] [32]
ARMv8-R Cortex-R52 TBD0–32 KB / 0–32 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24+24 regions2.09 DMIPS/MHz [33]
Cortex-R52+ TBD0–32 KB / 0–32 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24+24 regions2.09 DMIPS/MHz [34]
Cortex-R82 TBD16–128 KB /16–64 KB L1, 64K–1MB L2, 0.16–1 / 0.16–1 MB TCM,

opt MPU with 32+32 regions

3.41 DMIPS/MHz [35] [36]
Cortex-A
(32-bit) 		ARMv7-A Cortex-A5 Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)4−64 KB / 4−64 KB L1, MMU + TrustZone1.57 DMIPS/MHz per core [37]
Cortex-A7 Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), architecture and feature set are identical to A15, 8–10 stage pipeline, low-power design [38] 8−64 KB / 8−64 KB L1, 0–1 MB L2, MMU + TrustZone1.9 DMIPS/MHz per core [39]
Cortex-A8 Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stage superscalar pipeline16–32 KB / 16–32 KB L1, 0–1 MB L2 opt. ECC, MMU + TrustZoneUp to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1  GHz) [40]
Cortex-A9 Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)16–64 KB / 16–64 KB L1, 0–8 MB L2 opt. parity, MMU + TrustZone2.5 DMIPS/MHz per core, 10,000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G (dual-core) [41]
Cortex-A12 Application profile, ARM / Thumb-2 / DSP / VFPv4 FPU / NEON / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)32−64 KB3.0 DMIPS/MHz per core [42]
Cortex-A15 Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline [38] 32 KB w/parity / 32 KB w/ECC L1, 0–4 MB L2, L2 has ECC, MMU + TrustZoneAt least 3.5 DMIPS/MHz per core (up to 4.01 DMIPS/MHz depending on implementation) [43] [44]
Cortex-A17 Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP32 KB L1, 256 KB–8 MB L2 w/optional ECC2.8 DMIPS/MHz [45]
ARMv8-A Cortex-A32 Application profile, AArch32, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline8–64 KB w/optional parity / 8−64 KB w/optional ECC L1 per core, 128 KB–1 MB L2 w/optional ECC shared [46]
Cortex-A
(64-bit) 		ARMv8-A Cortex-A34 Application profile, AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–1 MB L2 shared, 40-bit physical addresses [47]
Cortex-A35 Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–1 MB L2 shared, 40-bit physical addresses1.78 DMIPS/MHz [48]
Cortex-A53 Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–2 MB L2 shared, 40-bit physical addresses2.3 DMIPS/MHz [49]
Cortex-A57 Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses4.1–4.8 DMIPS/MHz [50] [51] [52]
Cortex-A72 Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width superscalar, deeply out-of-order pipeline48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses6.3-7.3 DMIPS/MHz [53] [54]
Cortex-A73 Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width superscalar, deeply out-of-order pipeline64 KB / 32−64 KB L1 per core, 256 KB–8 MB L2 shared w/ optional ECC, 44-bit physical addresses7.4-8.5 DMIPS/MHz [53] [55]
ARMv8.2-A Cortex-A55 Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline [56] 16−64 KB / 16−64 KB L1, 256 KB L2 per core, 4 MB L3 shared3 DMIPS/MHz [53] [57]
Cortex-A65 Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, out-of-order pipeline, SMT [58]
Cortex-A65AE As ARM Cortex-A65, adds dual core lockstep for safety applications64 / 64 KB L1, 256 KB L2 per core, 4 MB L3 shared [59]
Cortex-A75 Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline [60] 64 / 64 KB L1, 512 KB L2 per core, 4 MB L3 shared8.2-9.5 DMIPS/MHz [53] [61]
Cortex-A76 Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way issue, 13 stage pipeline, deeply out-of-order pipeline [62] 64 / 64 KB L1, 256−512 KB L2 per core, 512 KB−4 MB L3 shared10.7-12.4 DMIPS/MHz [53] [63]
Cortex-A76AE As ARM Cortex-A76, adds dual core lockstep for safety applications [64]
Cortex-A77 Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 6-width instruction fetch, 12-way issue, 13 stage pipeline, deeply out-of-order pipeline [62] 1.5K L0 MOPs cache, 64 / 64 KB L1, 256−512 KB L2 per core, 512 KB−4 MB L3 shared13-16 DMIPS/MHz [65] [66]
Cortex-A78 [67]
Cortex-A78AE As ARM Cortex-A78, adds dual core lockstep for safety applications [68]
Cortex-A78C [69]
ARMv9-A Cortex-A510
Cortex-A710 [70]
Cortex-A715
Cortex-A520
Cortex-A720
Cortex-XARMv8.2-A Cortex-X1 Performance-tuned variant of Cortex-A78
ARMv9-A Cortex-X2
Cortex-X3
Cortex-X4
NeoverseARMv8.2-A Neoverse N1 Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way dispatch/issue, 13 stage pipeline, deeply out-of-order pipeline [62] 64 / 64 KB L1, 512−1024 KB L2 per core, 2−128 MB L3 shared, 128 MB system level cache [71]
Neoverse E1 Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, 10 stage pipeline, out-of-order pipeline, SMT 32−64 KB / 32−64 KB L1, 256 KB L2 per core, 4 MB L3 shared [72]
ARMv8.4-A Neoverse V1 [73]
ARMv9-A Neoverse N2 [74]
ARM familyARM architectureARM coreFeatureCache (I / D), MMU Typical MIPS @ MHzReference

Designed by third parties

These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.

Product familyARM architectureProcessorFeatureCache (I / D), MMU Typical MIPS @ MHz
StrongARM
(Digital)		ARMv4SA-1105-stage pipeline16 KB / 16 KB, MMU100–233 MHz
1.0 DMIPS/MHz
SA-1100derivative of the SA-11016 KB / 8 KB, MMU
Faraday [75]
(Faraday Technology)		ARMv4FA5106-stage pipelineUp to 32 KB / 32 KB cache, MPU1.26 DMIPS/MHz
100–200 MHz
FA526Up to 32 KB / 32 KB cache, MMU1.26 MIPS/MHz
166–300 MHz
FA6268-stage pipeline32 KB / 32 KB cache, MMU1.35 DMIPS/MHz
500 MHz
ARMv5TEFA606TE5-stage pipelineNo cache, no MMU1.22 DMIPS/MHz
200 MHz
FA626TE8-stage pipeline32 KB / 32 KB cache, MMU1.43 MIPS/MHz
800 MHz
FMP626TE8-stage pipeline, SMP1.43 MIPS/MHz
500 MHz
FA726TE13 stage pipeline, dual issue2.4 DMIPS/MHz
1000 MHz
XScale
(Intel / Marvell)		ARMv5TEXScale7-stage pipeline, Thumb, enhanced DSP instructions32 KB / 32 KB, MMU133–400 MHz
BulverdeWireless MMX, wireless SpeedStep added32 KB / 32 KB, MMU312–624 MHz
Monahans [76] Wireless MMX2 added32 KB / 32 KB L1, optional L2 cache up to 512 KB, MMUUp to 1.25 GHz
Sheeva
(Marvell)		ARMv5Feroceon5–8 stage pipeline, single-issue16 KB / 16 KB, MMU600–2000 MHz
Jolteon5–8 stage pipeline, dual-issue32 KB / 32 KB, MMU
PJ1 (Mohawk)5–8 stage pipeline, single-issue, Wireless MMX232 KB / 32 KB, MMU1.46 DMIPS/MHz
1.06 GHz
ARMv6 / ARMv7-APJ46–9 stage pipeline, dual-issue, Wireless MMX2, SMP32 KB / 32 KB, MMU2.41 DMIPS/MHz
1.6 GHz
Snapdragon
(Qualcomm)		ARMv7-A Scorpion [77] 1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON (128-bit wide)256 KB L2 per core2.1 DMIPS/MHz per core
Krait [77] 1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON (128-bit wide)4 KB / 4 KB L0, 16 KB / 16 KB L1, 512 KB L2 per core3.3 DMIPS/MHz per core
ARMv8-A Kryo [78] 4 cores. ?Up to 2.2 GHz

(6.3 DMIPS/MHz)

Ax
(Apple)		ARMv7-A Swift [79] 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEONL1: 32 KB / 32 KB, L2: 1 MB shared3.5 DMIPS/MHz per core
ARMv8-A Cyclone [80] 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64. Out-of-order, superscalar.L1: 64 KB / 64 KB, L2: 1 MB shared
SLC: 4 MB		1.3 or 1.4 GHz
ARMv8-A Typhoon [80] [81] 2 or 3 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64 L1: 64 KB / 64 KB, L2: 1 MB or 2 MB shared
SLC: 4 MB		1.4 or 1.5 GHz
ARMv8-A Twister [82] 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64 L1: 64 KB / 64 KB, L2: 2 MB shared
SLC: 4 MB or 0 MB		1.85 or 2.26 GHz
ARMv8-A Hurricane and Zephyr [83] Hurricane: 2 or 3 cores. AArch64, out-of-order, superscalar, 6-decode, 6-issue, 9-wide
Zephyr: 2 or 3 cores. AArch64, out-of-order, superscalar.		L1: 64 KB / 64 KB, L2: 3 MB or 8 MB shared
L1: 32 KB / 32 KB. L2: none
SLC: 4 MB or 0 MB		2.34 or 2.38 GHz
1.05 GHz
ARMv8.2-A Monsoon and Mistral [84] Monsoon: 2 cores. AArch64, out-of-order, superscalar, 7-decode, ?-issue, 11-wide
Mistral: 4 cores. AArch64, out-of-order, superscalar. Based on Swift.		L1I: 128 KB, L1D: 64 KB, L2: 8 MB shared
L1: 32 KB / 32 KB, L2: 1 MB shared
SLC: 4 MB		2.39 GHz
1.70 GHz
ARMv8.3-A Vortex and Tempest [85] Vortex: 2 or 4 cores. AArch64, out-of-order, superscalar, 7-decode, ?-issue, 11-wide
Tempest: 4 cores. AArch64, out-of-order, superscalar, 3-decode. Based on Swift.		L1: 128 KB / 128 KB, L2: 8 MB shared
L1: 32 KB / 32 KB, L2: 2 MB shared
SLC: 8 MB		2.49 GHz
1.59 GHz
ARMv8.4-A Lightning and Thunder [86] Lightning: 2 cores. AArch64, out-of-order, superscalar, 7-decode, ?-issue, 11-wide
Thunder: 4 cores. AArch64, out-of-order, superscalar.		L1: 128 KB / 128 KB, L2: 8 MB shared
L1: 32 KB / 48 KB, L2: 4 MB shared
SLC: 16 MB		2.66 GHz
1.73 GHz
ARMv8.5-A Firestorm and Icestorm [87] Firestorm: 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Icestorm: 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 7-wide.		L1: 192 KB / 128 KB, L2: 8 MB shared
L1: 128 KB / 64 KB, L2: 4 MB shared
SLC: 16 MB		3.0 GHz
1.82 GHz
ARMv8.5-A Avalanche and Blizzard Avalanche: 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Blizzard: 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.		L1: 192 KB / 128 KB, L2: 12 MB shared
L1: 128 KB / 64 KB, L2: 4 MB shared
SLC: 32 MB		2.93 or 3.23 GHz
2.02 GHz
ARMv8.5-A Everest and Sawtooth Everest: 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Sawtooth: 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.		L1: 192 KB / 128 KB, L2: 16 MB shared
L1: 128 KB / 64 KB, L2: 4 MB shared
SLC: 24 MB		3.46 GHz
2.02 GHz
Mx
(Apple)		ARMv8.4-A Firestorm and Icestorm Firestorm: 4, 6, 8 or 16 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Icestorm: 2 or 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 7-wide.		L1: 192 KB / 128 KB, L2: 12, 24 or 48 MB shared
L1: 128 KB / 64 KB, L2: 4 or 8 MB shared
SLC: 8, 24, 48 or 96 MB		3.2-3.23 GHz
2.06 GHz
ARMv8.5-A Avalanche and Blizzard Avalanche: 4, 6, 8 or 16 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Blizzard: 4 or 8 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.		L1: 192 KB / 128 KB, L2: 16, 32 or 64 MB shared
L1: 128 KB / 64 KB, L2: 4 or 8 MB shared
SLC: 8, 24, 48 or 96 MB		3.49 GHz
2.42 GHz
X-Gene
(Applied Micro)		ARMv8-AX-Gene64-bit, quad issue, SMP, 64 cores [88] Cache, MMU, virtualization3 GHz (4.2 DMIPS/MHz per core)
Denver
(Nvidia)		ARMv8-ADenver [89] [90] 2 cores. AArch64, 7-wide superscalar, in-order, dynamic code optimization, 128 MB optimization cache,
Denver1: 28 nm, Denver2:16 nm		128 KB I-cache / 64 KB D-cacheUp to 2.5 GHz
Carmel
(Nvidia)		ARMv8.2-ACarmel [91] [92] 2 cores. AArch64, 10-wide superscalar, in-order, dynamic code optimization, ? MB optimization cache,
functional safety, dual execution, parity & ECC		 ? KB I-cache / ? KB D-cacheUp to ? GHz
ThunderX
(Cavium)		ARMv8-AThunderX64-bit, with two models with 8–16 or 24–48 cores (×2 w/two chips) ?Up to 2.2 GHz
K12
(AMD)		ARMv8-AK12 [93]  ? ? ?
Exynos
(Samsung)		ARMv8-AM1 ("Mongoose") [94] 4 cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order64 KB I-cache / 32 KB D-cache, L2: 16-way shared 2 MB5.1 DMIPS/MHz

(2.6 GHz)

ARMv8-AM2 ("Mongoose")4 cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order64 KB I-cache / 32 KB D-cache, L2: 16-way shared 2 MB2.3 GHz
ARMv8-AM3 ("Meerkat") [95] 4 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order64 KB I-cache / 64 KB D-cache, L2: 8-way private 512 KB, L3: 16-way shared 4 MB2.7 GHz
ARMv8.2-AM4 ("Cheetah") [96] 2 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order64 KB I-cache / 64 KB D-cache, L2: 8-way private 1 MB, L3: 16-way shared 3 MB2.73 GHz
ARMv8.2-AM5 ("Lion")2 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order64 KB I-cache / 64 KB D-cache, L2: 8-way shared 2 MB, L3: 12-way shared 3 MB2.73 GHz

Timeline

The following table lists each core by the year it was announced. [97] [98]

YearClassic coresCortex coresNeoverse cores
ARM1-6 ARM7 ARM8 ARM9 ARM10 ARM11 Microcontroller Real-time Application
(32-bit)		 Application
(64-bit)		Application
(64-bit)
1985ARM1
1986ARM2
1989ARM3
1992ARM250
1993ARM60
ARM610		ARM700
1994ARM710
ARM7DI
ARM7TDMI
1995ARM710a
1996ARM810
1997ARM710T
ARM720T
ARM740T
1998ARM9TDMI
ARM940T
1999ARM9E-S
ARM966E-S
2000ARM920T
ARM922T
ARM946E-S		ARM1020T
2001ARM7TDMI-S
ARM7EJ-S		ARM9EJ-S
ARM926EJ-S		ARM1020E
ARM1022E
2002ARM1026EJ-SARM1136J(F)-S
2003ARM968E-SARM1156T2(F)-S
ARM1176JZ(F)-S
2004Cortex-M3
2005ARM11MPCoreCortex-A8
2006ARM996HS
2007Cortex-M1Cortex-A9
2008
2009Cortex-M0Cortex-A5
2010Cortex-M4(F)Cortex-A15
2011Cortex-R4
Cortex-R5
Cortex-R7		Cortex-A7
2012Cortex-M0+Cortex-A53
Cortex-A57
2013Cortex-A12
2014Cortex-M7(F)Cortex-A17
2015Cortex-A35
Cortex-A72
2016Cortex-M23
Cortex-M33(F)		Cortex-R8
Cortex-R52		Cortex-A32Cortex-A73
2017Cortex-A55
Cortex-A75
2018Cortex-M35P(F)Cortex-A65AE
Cortex-A76
Cortex-A76AE
2019Cortex-A77Neoverse E1
Neoverse N1
2020Cortex-M55(F)Cortex-R82Cortex-A78
Cortex-X1 [99] 		Neoverse V1 [100]
2021Cortex-A510
Cortex-A710
Cortex-X2		Neoverse N2
2022Cortex-M85(F)Cortex-R52+Cortex-A715
Cortex-X3
2023Cortex-M52(F)Cortex-A520
Cortex-A720
Cortex-X4
2024Cortex-R82AECortex-A520AE
Cortex-A720AE
Neoverse N3
Neoverse V3
Neoverse V3AE

See also

Related Research Articles

<span class="mw-page-title-main">Instructions per second</span> Measure of a computers processing speed

Instructions per second (IPS) is a measure of a computer's processor speed. For complex instruction set computers (CISCs), different instructions take different amounts of time, so the value measured depends on the instruction mix; even for comparing processors in the same family the IPS measurement can be problematic. Many reported IPS values have represented "peak" execution rates on artificial instruction sequences with few branches and no cache contention, whereas realistic workloads typically lead to significantly lower IPS values. Memory hierarchy also greatly affects processor performance, an issue barely considered in IPS calculations. Because of these problems, synthetic benchmarks such as Dhrystone are now generally used to estimate computer performance in commonly used applications, and raw IPS has fallen into disuse.

ARM is a family of RISC instruction set architectures (ISAs) for computer processors. Arm Ltd. develops the ISAs and licenses them to other companies, who build the physical devices that use the instruction set. It also designs and licenses cores that implement these ISAs.

<span class="mw-page-title-main">Tegra</span> System on a chip by Nvidia

Tegra is a system on a chip (SoC) series developed by Nvidia for mobile devices such as smartphones, personal digital assistants, and mobile Internet devices. The Tegra integrates an ARM architecture central processing unit (CPU), graphics processing unit (GPU), northbridge, southbridge, and memory controller onto one package. Early Tegra SoCs are designed as efficient multimedia processors. The Tegra-line evolved to emphasize performance for gaming and machine learning applications without sacrificing power efficiency, before taking a drastic shift in direction towards platforms that provide vehicular automation with the applied "Nvidia Drive" brand name on reference boards and its semiconductors; and with the "Nvidia Jetson" brand name for boards adequate for AI applications within e.g. robots or drones, and for various smart high level automation purposes.

<span class="mw-page-title-main">Qualcomm Snapdragon</span> Suite of system-on-a-chip (SoC) semiconductor products

Snapdragon is a suite of system on a chip (SoC) semiconductor products for mobile devices designed and marketed by Qualcomm Technologies Inc. The Snapdragon's central processing unit (CPU) uses the ARM architecture. As such, Qualcomm often refers to the Snapdragon as a "mobile platform". Snapdragon semiconductors are embedded in devices of various systems, including vehicles, Android, Windows Phone and netbooks. In addition to the processors, the Snapdragon line includes modems, Wi-Fi chips and mobile charging products.

<span class="mw-page-title-main">Arm Holdings</span> British multinational semiconductor and software design company

Arm Holdings plc is a British semiconductor and software design company based in Cambridge, England, whose primary business is the design of central processing unit (CPU) cores that implement the ARM architecture family of instruction sets. It also designs other chips, provides software development tools under the DS-5, RealView and Keil brands, and provides systems and platforms, system-on-a-chip (SoC) infrastructure and software. As a "holding" company, it also holds shares of other companies. Since 2016, it has been majority owned by Japanese conglomerate SoftBank Group.

<span class="mw-page-title-main">Nexus S</span> 2010 smartphone by Google and Samsung

The Nexus S is a smartphone co-developed by Google and Samsung and manufactured by Samsung Electronics for release in 2010. It was the first smartphone to use the Android 2.3 "Gingerbread" operating system, and the first Android device to support Near Field Communication (NFC) in both hardware and software.

<span class="mw-page-title-main">ARM Cortex-A15</span> Family of microprocessor cores with ARM microarchitecture

The ARM Cortex-A15 MPCore is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. It is a multicore processor with out-of-order superscalar pipeline running at up to 2.5 GHz.

<span class="mw-page-title-main">Apple A5</span> System on a chip (SoC) designed by Apple Inc.

The Apple A5 is a 32-bit system on a chip (SoC) designed by Apple Inc. and manufactured by Samsung. The first product Apple featured an A5 in was the iPad 2. Apple claimed during their media event on March 2, 2011, that the ARM Cortex-A9 central processing unit (CPU) in the A5 is up to two times faster than the CPU in the Apple A4, and the PowerVR SGX543MP2 graphics processing unit (GPU) in the A5 is up to nine times faster than the GPU in the A4. Apple also claimed that the A5 uses the same amount of power as the A4.

<span class="mw-page-title-main">Apple silicon</span> System-on-chip processors designed by Apple Inc.

Apple silicon refers to a series of system on a chip (SoC) and system in a package (SiP) processors designed by Apple Inc., mainly using the ARM architecture. They are the basis of Mac, iPhone, iPad, Apple TV, Apple Watch, AirPods, AirTag, HomePod, and Apple Vision Pro devices.

<span class="mw-page-title-main">Exynos</span> Family of ARM based system-on-a-chip models

Exynos, formerly Hummingbird (Korean: 엑시노스), is a series of ARM-based system-on-chips developed by Samsung Electronics' System LSI division and manufactured by Samsung Foundry. It is a continuation of Samsung's earlier S3C, S5L and S5P line of SoCs.

The ARM Cortex-A5 is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture announced in 2009.

<span class="mw-page-title-main">ARM Cortex-A7</span> 2011 computer microprocessor core

The ARM Cortex-A7 MPCore is a 32-bit microprocessor core licensed by ARM Holdings implementing the ARMv7-A architecture announced in 2011.

<span class="mw-page-title-main">Mali (processor)</span> Series of graphics processing units produced by ARM Holdings

The Mali and Immortalis series of graphics processing units (GPUs) and multimedia processors are semiconductor intellectual property cores produced by Arm Holdings for licensing in various ASIC designs by Arm partners.

<span class="mw-page-title-main">Apple A6</span> System on a chip (SoC) designed by Apple Inc.

The Apple A6 is a 32-bit package on package (PoP) system on a chip (SoC) designed by Apple Inc. that was introduced on September 12, 2012, at the launch of the iPhone 5. Apple states that it is up to twice as fast and has up to twice the graphics power compared with its predecessor, the Apple A5. Software updates for devices using this chip ceased in 2019, with the release of iOS 10.3.4 on the iPhone 5 as it was discontinued with the release of iOS 11 in 2017.

<span class="mw-page-title-main">ARM big.LITTLE</span> Heterogeneous computing architecture

ARM big.LITTLE is a heterogeneous computing architecture developed by ARM Holdings, coupling relatively battery-saving and slower processor cores (LITTLE) with relatively more powerful and power-hungry ones (big). The intention is to create a multi-core processor that can adjust better to dynamic computing needs and use less power than clock scaling alone. ARM's marketing material promises up to a 75% savings in power usage for some activities. Most commonly, ARM big.LITTLE architectures are used to create a multi-processor system-on-chip (MPSoC).

The ARM Cortex-A17 is a 32-bit processor core implementing the ARMv7-A architecture, licensed by ARM Holdings. Providing up to four cache-coherent cores, it serves as the successor to the Cortex-A9 and replaces the previous ARM Cortex-A12 specifications. ARM claims that the Cortex-A17 core provides 60% higher performance than the Cortex-A9 core, while reducing the power consumption by 20% under the same workload.

This is a comparison of ARM instruction set architecture application processor cores designed by ARM Holdings and 3rd parties. It does not include ARM Cortex-R, ARM Cortex-M, or legacy ARM cores.

The ARM Cortex-A76 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre. ARM states a 25% and 35% increase in integer and floating point performance, respectively, over a Cortex-A75 of the previous generation.

The ARM Cortex-A78 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Ltd.'s Austin centre.

The ARM Neoverse is a group of 64-bit ARM processor cores licensed by Arm Holdings. The cores are intended for datacenter, edge computing, and high-performance computing use. The group consists of ARM Neoverse V-Series, ARM Neoverse N-Series, and ARM Neoverse E-Series.

References

  1. ↑ "ARM Powered Standard Products" (PDF). 2005. Archived from the original (PDF) on 20 October 2017. Retrieved 23 December 2017.
  2. ↑ ARM Ltd and ARM Germany GmbH. "Device Database". Keil. Archived from the original on 10 January 2011. Retrieved 6 January 2011.
  3. ↑ "Processors". ARM. 2011. Archived from the original on 17 January 2011. Retrieved 6 January 2011.
  4. ↑ "ARM610 Datasheet" (PDF). ARM Holdings . August 1993. Retrieved 29 January 2019.
  5. ↑ "ARM710 Datasheet" (PDF). ARM Holdings . July 1994. Retrieved 29 January 2019.
  6. ↑ ARM Holdings (7 August 1996). "ARM810 – Dancing to the Beat of a Different Drum" (PDF). Hot Chips. Archived (PDF) from the original on 24 December 2018. Retrieved 14 November 2018.
  7. ↑ "VLSI Technology Now Shipping ARM810". EE Times . 26 August 1996. Archived from the original on 26 September 2013. Retrieved 21 September 2013.
  8. ↑ Register 13, FCSE PID register Archived 7 July 2011 at the Wayback Machine ARM920T Technical Reference Manual
  9. ↑ "ARM1136J(F)-S – ARM Processor". Arm.com. Archived from the original on 21 March 2009. Retrieved 18 April 2009.
  10. ↑ "ARM1156 Processor". Arm Holdings. Archived from the original on 13 February 2010.
  11. ↑ "ARM11 Processor Family". ARM. Archived from the original on 15 January 2011. Retrieved 12 December 2010.
  12. 1 2 3 "Cortex-M0/M0+/M1 Instruction set; ARM Holding". Archived from the original on 18 April 2013.
  13. ↑ "Cortex-M0". Arm Developer. Retrieved 23 September 2020.
  14. ↑ "Cortex-M0+". Arm Developer. Retrieved 23 September 2020.
  15. ↑ "ARM Extends Cortex Family with First Processor Optimized for FPGA" (Press release). ARM Holdings. 19 March 2007. Archived from the original on 5 May 2007. Retrieved 11 April 2007.
  16. ↑ "ARM Cortex-M1". ARM product website. Archived from the original on 1 April 2007. Retrieved 11 April 2007.
  17. ↑ "Cortex-M1". Arm Developer. Retrieved 23 September 2020.
  18. ↑ "Cortex-M3". Arm Developer. Retrieved 23 September 2020.
  19. ↑ "Cortex-M4". Arm Developer. Retrieved 23 September 2020.
  20. ↑ "Cortex-M7". Arm Developer. Retrieved 23 September 2020.
  21. ↑ "Cortex-M23". Arm Developer. Retrieved 23 September 2020.
  22. ↑ "Cortex-M33". Arm Developer. Retrieved 23 September 2020.
  23. ↑ "Cortex-M35P". Arm Developer. Archived from the original on 8 May 2019. Retrieved 29 April 2019.
  24. ↑ "Cortex-M52". Arm Developer. Retrieved 23 November 2023.
  25. ↑ "Cortex-M55". Arm Developer. Retrieved 28 September 2020.
  26. ↑ "Cortex-M85". Arm Developer. Retrieved 7 July 2022.
  27. 1 2 3 4 "Cortex-R – Arm Developer". ARM Developer. Arm Ltd. Archived from the original on 30 March 2018. Retrieved 29 March 2018.
  28. ↑ "Cortex-R4". Arm Developer. Retrieved 23 September 2020.
  29. 1 2 "Cortex-R5 & Cortex-R7 Press Release; ARM Holdings; 31 January 2011". Archived from the original on 7 July 2011. Retrieved 13 June 2011.
  30. ↑ "Cortex-R5". Arm Developer. Retrieved 23 September 2020.
  31. ↑ "Cortex-R7". Arm Developer. Retrieved 23 September 2020.
  32. ↑ "Cortex-R8". Arm Developer. Retrieved 23 September 2020.
  33. ↑ "Cortex-R52". Arm Developer. Archived from the original on 23 November 2023. Retrieved 23 November 2023.
  34. ↑ "Cortex-R52". Arm Developer. Archived from the original on 23 November 2023. Retrieved 23 November 2023.
  35. ↑ "Cortex-R82". Arm Developer. Retrieved 30 September 2020.
  36. ↑ "Arm Cortex-R comparison Table_v2" (PDF). ARM Developer. 2020. Retrieved 30 September 2020.
  37. ↑ "Cortex-A5". Arm Developer. Retrieved 23 September 2020.
  38. 1 2 "Deep inside ARM's new Intel killer". The Register. 20 October 2011. Archived from the original on 10 August 2017. Retrieved 10 August 2017.
  39. ↑ "Cortex-A7". Arm Developer. Retrieved 23 September 2020.
  40. ↑ "Cortex-A8". Arm Developer. Retrieved 23 September 2020.
  41. ↑ "Cortex-A9". Arm Developer. Retrieved 23 September 2020.
  42. ↑ "Cortex-A12 Summary; ARM Holdings". Archived from the original on 7 June 2013. Retrieved 3 June 2013.
  43. ↑ "Exclusive : ARM Cortex-A15 "40 Per Cent" Faster Than Cortex-A9 | ITProPortal.com". Archived from the original on 21 July 2011. Retrieved 13 June 2011.
  44. ↑ "Cortex-A15". Arm Developer. Retrieved 23 September 2020.
  45. ↑ "Cortex-A17". Arm Developer. Retrieved 23 September 2020.
  46. ↑ "Cortex-A32". Arm Developer. Retrieved 23 September 2020.
  47. ↑ "Cortex-A34". Arm Developer. Retrieved 11 October 2019.
  48. ↑ "Cortex-A35". Arm Developer. Retrieved 23 September 2020.
  49. ↑ "Cortex-A53". Arm Developer. Retrieved 23 September 2020.
  50. ↑ "Cortex-Ax vs performance". Archived from the original on 15 June 2017. Retrieved 5 May 2017.
  51. ↑ "Relative Performance of ARM Cortex-A 32-bit and 64-bit Cores". 9 April 2015. Archived from the original on 1 May 2017. Retrieved 5 May 2017.
  52. ↑ "Cortex-A57". Arm Developer. Retrieved 23 September 2020.
  53. 1 2 3 4 5 Sima, Dezső (November 2018). "ARM's processor lines" (PDF). University of Óbuda, Neumann Faculty. Retrieved 26 May 2022.
  54. ↑ "Cortex-A72". Arm Developer. Retrieved 23 September 2020.
  55. ↑ "Cortex-A73". Arm Developer. Retrieved 23 September 2020.
  56. ↑ "Hardware.Info Nederland". nl.hardware.info (in Dutch). Archived from the original on 24 December 2018. Retrieved 27 November 2017.
  57. ↑ "Cortex-A55". Arm Developer. Retrieved 23 September 2020.
  58. ↑ "Cortex-A65". Arm Developer. Retrieved 3 October 2020.
  59. ↑ "Cortex-A65AE". Arm Developer. Retrieved 11 October 2019.
  60. ↑ "Hardware.Info Nederland". nl.hardware.info (in Dutch). Archived from the original on 24 December 2018. Retrieved 27 November 2017.
  61. ↑ "Cortex-A75". Arm Developer. Retrieved 23 September 2020.
  62. 1 2 3 "Arm's Cortex-A76 CPU Unveiled: Taking Aim at the Top for 7nm". AnandTech. Archived from the original on 16 November 2018. Retrieved 15 November 2018.
  63. ↑ "Cortex-A76". Arm Developer. Retrieved 23 September 2020.
  64. ↑ "Cortex-A76AE". Arm Developer. Retrieved 29 September 2020.
  65. ↑ According to ARM, the Cortex-A77 has a 20% IPC single-thread performance improvement over its predecessor in Geekbench 4, 23% in SPECint2006, 35% in SPECfp2006, 20% in SPECint2017, and 25% in SPECfp2017
  66. ↑ "Cortex-A77". Arm Developer. Retrieved 16 June 2019.
  67. ↑ "Cortex-A78". Arm Developer. Retrieved 29 September 2020.
  68. ↑ "Cortex-A78AE". Arm Developer. Retrieved 30 September 2020.
  69. ↑ "Cortex-A78C". Arm Developer. Retrieved 26 November 2020.
  70. ↑ "First Armv9 Cortex CPUs for Consumer Compute". community.arm.com. Retrieved 24 August 2021.
  71. ↑ "Neoverse N1". Arm Developer. Retrieved 16 June 2019.
  72. ↑ "Neoverse E1". Arm Developer. Retrieved 3 October 2020.
  73. ↑ "Neoverse V1". developer.arm.com. Retrieved 30 August 2022.
  74. ↑ "Neoverse N2". developer.arm.com. Retrieved 30 August 2022.
  75. ↑ "Processor Cores". Faraday Technology. Archived from the original on 19 February 2015. Retrieved 19 February 2015.
  76. ↑ "3rd Generation Intel XScale Microarchitecture: Developer's Manual" (PDF). download.intel.com. Intel. May 2007. Archived (PDF) from the original on 25 February 2008. Retrieved 2 December 2010.
  77. 1 2 "Qualcomm's New Snapdragon S4: MSM8960 & Krait Architecture Explored". AnandTech . Retrieved 23 September 2020.
  78. ↑ "Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute". Qualcomm. 2 September 2015. Archived from the original on 5 September 2015. Retrieved 6 September 2015.
  79. ↑ Lal Shimpi, Anand (15 September 2012). "The iPhone 5's A6 SoC: Not A15 or A9, a Custom Apple Core Instead". AnandTech. Archived from the original on 15 September 2012. Retrieved 15 September 2012.
  80. 1 2 Smith, Ryan (11 November 2014). "Apple A8X's GPU - GAX6850, Even Better Than I Thought". AnandTech . Archived from the original on 30 November 2014. Retrieved 29 November 2014.
  81. ↑ Chester, Brandon (15 July 2015). "Apple Refreshes The iPod Touch With A8 SoC And New Cameras". AnandTech . Archived from the original on 5 September 2015. Retrieved 11 September 2015.
  82. ↑ Ho, Joshua (28 September 2015). "iPhone 6s and iPhone 6s Plus Preliminary Results". AnandTech . Archived from the original on 26 May 2016. Retrieved 18 December 2015.
  83. ↑ Ho, Joshua (28 September 2015). "The iPhone 7 and iPhone 7 Plus Review". AnandTech . Archived from the original on 14 September 2017. Retrieved 14 September 2017.
  84. ↑ "A11 Bionic - Apple". WikiChip. Retrieved 1 February 2019.
  85. ↑ "The iPhone XS & XS Max Review: Unveiling the Silicon Secrets". AnandTech . Archived from the original on 12 February 2019. Retrieved 11 February 2019.
  86. ↑ Frumusanu, Andrei. "The Apple iPhone 11, 11 Pro & 11 Pro Max Review: Performance, Battery, & Camera Elevated". AnandTech . Retrieved 20 October 2019.
  87. ↑ Frumusanu, Andrei. "The iPhone 12 & 12 Pro Review: New Design and Diminishing Returns". AnandTech . Retrieved 5 April 2021.
  88. ↑ "AppliedMicro's 64-core chip could spark off ARM core war copy". 12 August 2014. Archived from the original on 21 August 2014. Retrieved 21 August 2014.
  89. ↑ "NVIDIA Denver Hot Chips Disclosure". Archived from the original on 5 December 2014. Retrieved 29 November 2014.
  90. ↑ "Mile High Milestone: Tegra K1 "Denver" Will Be First 64-bit ARM Processor for Android". Archived from the original on 12 August 2014. Retrieved 29 November 2014.
  91. ↑ "Drive Xavier für autonome Autos wird ausgeliefert" (in German). Archived from the original on 5 March 2018. Retrieved 5 March 2018.
  92. ↑ "NVIDIA Drive Xavier SOC Detailed – A Marvel of Engineering, Biggest and Most Complex SOC Design To Date With 9 Billion Transistors". 8 January 2018. Archived from the original on 24 February 2018. Retrieved 5 March 2018.
  93. ↑ "AMD Announces K12 Core: Custom 64-bit ARM Design in 2016". Archived from the original on 26 June 2015. Retrieved 26 June 2015.
  94. ↑ "Samsung Announces Exynos 8890 with Cat.12/13 Modem and Custom CPU". AnandTech . Retrieved 23 September 2020.
  95. ↑ "Hot Chips 2018: Samsung's Exynos-M3 CPU Architecture Deep Dive". AnandTech. Archived from the original on 20 August 2018. Retrieved 20 August 2018.
  96. ↑ "ISCA 2020: Evolution of the Samsung Exynos CPU Microarchitecture". AnandTech. 3 June 2020. Retrieved 27 December 2021.
  97. ↑ "ARM Company Milestones". Archived from the original on 28 March 2014. Retrieved 6 April 2014.
  98. ↑ "ARM Press Releases". Archived from the original on 9 April 2014. Retrieved 6 April 2014.
  99. ↑ "Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence".
  100. ↑ "Arm Announces Neoverse V1 & N2 Infrastructure CPUs: +50% IPC, SVE Server Cores". Anandtech. 22 September 2020. Retrieved 15 April 2021.

Further reading

This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.