Comparison of ARM processors

Last updated

This is a comparison of ARM instruction set architecture application processor cores designed by ARM Holdings (ARM Cortex-A) and 3rd parties. It does not include ARM Cortex-R, ARM Cortex-M, or legacy ARM cores.

Contents

ARMv7-A

This is a table comparing 32-bit central processing units that implement the ARMv7-A (A means Application [1] ) instruction set architecture and mandatory or optional extensions of it, the last AArch32.

CoreDecode
width		Execution
ports		 Pipeline
depth		 Out-of-order execution FPU Pipelined
VFP		FPU
registers		 NEON
(SIMD)		 big.LITTLE
role		Virtualization [2] Process
technology 		L0
cache		L1
cache		L2
cache		Core
configurations		Speed
per
core
(DMIPS
/ MHz)		ARM part number
(in the main ID register)
ARM Cortex-A5 18NoVFPv4 (optional)16 × 64-bit64-bit wide (optional)NoNo40/28 nm4–64  KiB / core1, 2, 41.570xC05
ARM Cortex-A7 25 [3] 8NoVFPv4Yes16 × 64-bit64-bit wideLITTLEYes [4] 40/28 nm8–64 KiB / coreup to 1  MiB (optional)1, 2, 4, 81.90xC07
ARM Cortex-A8 22 [5] 13NoVFPv3No32 × 64-bit64-bit wideNoNo65/55/45 nm32 KiB + 32 KiB256 or 512 (typical) KiB12.00xC08
ARM Cortex-A9 23 [6] 8–11 [7] YesVFPv3 (optional)Yes(16 or 32) × 64-bit64-bit wide (optional)Companion CoreNo [7] 65/45/40/32/28 nm32 KiB + 32 KiB1 MiB1, 2, 42.50xC09
ARM Cortex-A12 211YesVFPv4Yes32 × 64-bit128-bit wideNo [8] Yes28 nm32–64 KiB + 32 KiB256 KiB, to 8 MiB1, 2, 43.00xC0D
ARM Cortex-A15 38 [3] 15/17-25YesVFPv4Yes32 × 64-bit128-bit widebigYes [9] 32/28/20 nm32 KiB + 32 KiB per coreup to 4 MiB per cluster, up to 8 MiB per chip2, 4, 8 (4×2)3.5 to 4.010xC0F
ARM Cortex-A17 2 [10] 11+YesVFPv4Yes32 × 64-bit128-bit widebigYes28 nm32 KiB + 32 KiB per core256 KiB, up to 8 MiBup to 44.00xC0E
Qualcomm Scorpion 23 [11] 10Yes (FXU&LSU only) [12] VFPv3Yes128-bit wideNo 65/45 nm 32 KiB + 32 KiB256 KiB (single-core)
512 KiB (dual-core)		1, 22.10x00F
Qualcomm Krait [13] 3711YesVFPv4 [14] Yes128-bit wideNo28 nm4 KiB + 4 KiB direct mapped16 KiB + 16 KiB 4-way set associative1 MiB 8-way set associative (dual-core) / 2 MiB (quad-core)2, 43.3 (Krait 200)
3.39 (Krait 300)
3.39 (Krait 400)
3.51 (Krait 450)		0x04D

0x06F
Swift 3512YesVFPv4Yes32 × 64-bit128-bit wideNo32 nm32 KiB + 32 KiB1 MiB23.5?
CoreDecode
width		Execution
ports		 Pipeline
depth		 Out-of-order execution FPU Pipelined
VFP		FPU
registers		 NEON
(SIMD)		 big.LITTLE
role		Virtualization [2] Process
technology 		L0
cache		L1
cache		L2
cache		Core
configurations		Speed
per
core
(DMIPS
/ MHz)		ARM part number
(in the main ID register)

ARMv8-A

This is a table of 64/32-bit central processing units that implement the ARMv8-A instruction set architecture and mandatory or optional extensions of it. Most chips support the 32-bit ARMv7-A for legacy applications. All chips of this type have a floating-point unit (FPU) that is better than the one in older ARMv7-A and NEON (SIMD) chips. Some of these chips have coprocessors also include cores from the older 32-bit architecture (ARMv7). Some of the chips are SoCs and can combine both ARM Cortex-A53 and ARM Cortex-A57, such as the Samsung Exynos 7 Octa.

CompanyCoreReleasedRevisionDecode Pipeline
depth		 Out-of-order
execution 		Branch
prediction 		big.LITTLE roleExec.
ports		 SIMD Fab
(in nm)		 Simult. MT L0 cache L1 cache
Instr  +  Data
(in KiB)		L2 cacheL3 cacheCore
configu-
rations		Speed per core (DMIPS/
MHz [note 1] )		 Clock rate ARM part number (in the main ID register)
Have itEntries
ARM Cortex-A32 (32-bit) [15] 2017ARMv8.0-A
(only 32-bit)		2-wide8No0?LITTLE??28 [16] NoNo8–64 + 8–640–1 MiBNo1–4+??0xD01
Cortex-A34 (64-bit) [17] 2019ARMv8.0-A
(only 64-bit)		2-wide8No0?LITTLE???NoNo8–64 + 8–640–1 MiBNo1–4+??0xD02
Cortex-A35 [18] 2017ARMv8.0-A2-wide [19] 8No0YesLITTLE??28 / 16 /
14 / 10		NoNo8–64 + 8–640 / 128 KiB–1 MiBNo1–4+1.78?0xD04
Cortex-A53 [20] 2014ARMv8.0-A2-wide8No0Conditional+
Indirect branch
prediction		big/LITTLE2?28 / 20 /
16 / 14 / 10		NoNo8–64 + 8–64128 KiB–2 MiBNo1–4+2.24?0xD03
Cortex-A55 [21] 2017ARMv8.2-A2-wide8No0big/LITTLE2?28 / 20 /
16 / 14 / 12 / 10 / 5 [22] 		NoNo16–64 + 16–640–256 KiB/core0–4 MiB1–8+2.65 [23] ?0xD05
Cortex-A57 [24] 2013ARMv8.0-A3-wide15Yes
3-wide dispatch		??big8?28 / 20 /
16 [25]  / 14		NoNo48 + 320.5–2 MiBNo1–4+4.8?0xD07
Cortex-A65 [26] 2019ARMv8.2-A
(only 64-bit)		2-wide10-12Yes
4-wide dispatch		Two-level?9?SMT2No32–64 + 32–64 KiB0, 64–256 KiB0, 0.5–4 MiB1-8??0xD06
Cortex-A65AE [27] 2019ARMv8.2-A??YesTwo-level?2?SMT2No32–64 + 32–64 KiB64–256 KiB0, 0.5–4 MiB1–8??0xD43
Cortex-A72 [28] 2015ARMv8.0-A3-wide15Yes
5-wide dispatch		Two-levelbig828 / 16NoNo48 + 320.5–4 MiBNo1–4+6.3–7.3 [29] ?0xD08
Cortex-A73 [30] 2016ARMv8.0-A2-wide11–12Yes
4-wide dispatch		Two-levelbig728 / 16 / 10NoNo64 + 32/641–8 MiBNo1–4+7.4–8.5 [29] ?0xD09
Cortex-A75 [21] 2017ARMv8.2-A3-wide11–13Yes
6-wide dispatch		Two-levelbig8?2*128b28 / 16 / 10NoNo64 + 64256–512 KiB/core0–4 MiB1–8+8.2–9.5 [29] ?0xD0A
Cortex-A76 [31] 2018ARMv8.2-A4-wide11–13Yes
8-wide dispatch		128Two-levelbig82*128b10 / 7NoNo64 + 64256–512 KiB/core1–4 MiB1–410.7–12.4 [29] ?0xD0B
Cortex-A76AE [32] 2018ARMv8.2-A??Yes128Two-levelbig??NoNo??????0xD0E
Cortex-A77 [33] 2019ARMv8.2-A4-wide11–13Yes
10-wide dispatch		160Two-levelbig122*128b7No1.5K entries64 + 64256–512 KiB/core1–4 MiB1–413–16 [34] ?0xD0D
Cortex-A78 [35] [36] 2020ARMv8.2-A4-wideYes160Yesbig132*128bNo1.5K entries32/64 + 32/64256–512 KiB/core1–4 MiB1–4??0xD41
Cortex-X1 [37] 2020ARMv8.2-A5-wide [37] ?Yes224Yesbig154*128bNo3K entries64 + 64up to 1 MiB [37] up to 8 MiB [37] custom [37] ??0xD44
Apple Cyclone [38] 2013ARMv8.0-A6-wide [39] 16 [39] Yes [39] 192YesNo9 [39] 28 [40] NoNo64 + 64 [39] 1 MiB [39] 4 MiB [39] 2 [41] ?1.3–1.4 GHz
Typhoon 2014ARMv8.0‑A6-wide [42] 16 [42] Yes [42] YesNo920NoNo64 + 64 [39] 1 MiB [42] 4 MiB [39] 2, 3 (A8X)?1.1–1.5 GHz
Twister 2015ARMv8.0‑A6-wide [42] 16 [42] Yes [42] YesNo916 / 14NoNo64 + 64 [42] 3 MiB [42] 4 MiB [42]
No (A9X)		2?1.85–2.26 GHz
Hurricane 2016ARMv8.0‑A6-wide [43] 16Yes"big" (In A10/A10X paired with "LITTLE" Zephyr
cores)		93*128b16 (A10)
10 (A10X)		NoNo64 + 64 [44] 3 MiB [44] (A10)
8 MiB (A10X)		4 MiB [44] (A10)
No (A10X)		2x Hurricane (A10)
3x Hurricane (A10X)		?2.34–2.36 GHz
Zephyr ARMv8.0‑A3-wide12YesLITTLE516 (A10)
10 (A10X)		NoNo32 + 32 [45] 1 MiB4 MiB [44] (A10)
No (A10X)		2x Zephyr (A10)
3x Zephyr (A10X)		?1.09–1.3 GHz
Monsoon 2017ARMv8.2‑A [46] 7-wide16Yes"big" (In Apple A11 paired with "LITTLE" Mistral
cores)		113*128b10NoNo64 + 64 [45] 8 MiBNo2x Monsoon ?2.39 GHz
Mistral ARMv8.2‑A [46] 3-wide12YesLITTLE510NoNo32 + 32 [45] 1 MiBNo4× Mistral ?1.19 GHz
Vortex 2018ARMv8.3‑A [47] 7-wide16Yes"big" (In Apple A12/Apple A12X/Apple A12Z paired with "LITTLE" Tempest
cores)		113*128b7NoNo128 + 128 [45] 8 MiBNo2x Vortex (A12)
4x Vortex (A12X/A12Z)		?2.49 GHz
Tempest ARMv8.3‑A [47] 3-wide12YesLITTLE57NoNo32 + 32 [45] 2 MiBNo4x Tempest ?1.59 GHz
Lightning 2019ARMv8.4‑A [48] 8-wide16Yes560"big" (In Apple A13 paired with "LITTLE" Thunder
cores)		113*128b7NoNo128 + 128 [49] 8 MiBNo2x Lightning ?2.65 GHz
Thunder ARMv8.4‑A [48] 3-wide12YesLITTLE57NoNo96 + 48 [50] 4 MiBNo4x Thunder ?1.8 GHz
Firestorm 2020ARMv8.4-A [51] 8-wide [52] Yes630 [53] "big" (In Apple A14 and Apple M1/M1 Pro/M1 Max/M1 Ultra paired with "LITTLE" Icestorm
cores)		144*128b5No192 + 1288 MiB (A14)
12 MiB (M1)
24 MiB (M1 Pro/M1 Max)
48 MiB (M1 Ultra)		No2x Firestorm (A14)
4x Firestorm (M1)

6x or 8x Firestorm (M1 Pro)
8x Firestorm (M1 Max)
16x Firestorm (M1 Ultra)

?3.0–3.23 GHz
Icestorm ARMv8.4-A [51] 4-wideYes110LITTLE72*128b5No128 + 644 MiB
8 MiB (M1 Ultra)		No4x Icestorm (A14/M1)
2x Icestorm (M1 Pro/Max)
4x Icestorm (M1 Ultra)		?1.82–2.06 GHz
Avalanche 2021ARMv8.6‑A [51] 8-wideYes"big" (In Apple A15 and Apple M2/M2 Pro/M2 Max/M2 Ultra paired with "LITTLE" Blizzard
cores)		144*128b5No192 + 12812 MiB (A15)
16 MiB (M2)
32 MiB (M2 Pro/M2 Max)
64 MiB (M2 Ultra)		No2x Avalanche (A15)
4x Avalanche (M2)
6x or 8x Avalanche (M2 Pro)

8x Avalanche (M2 Max)
16x Avalanche (M2 Ultra)

?2.93–3.49 GHz
Blizzard ARMv8.6‑A [51] 4-wideYesLITTLE82*128b5No128 + 644 MiB
8 MiB (M2 Ultra)		No4x Blizzard ?2.02–2.42 GHz
Everest 2022ARMv8.6‑A [51] 8-wideYes"big" (In Apple A16 paired with "LITTLE" Sawtooth
cores)		144*128b5No192 + 12816 MiBNo2x Everest ?3.46 GHz
Sawtooth ARMv8.6‑A [51] 4-wideYesLITTLE82*128b5No128 + 644 MiBNo4x Sawtooth ?2.02 GHz
Nvidia Denver [54] [55] 2014ARMv8‑A2-wide hardware
decoder, up to
7-wide variable-
length VLIW
micro-ops		13Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW.		Direct+
Indirect branch
prediction		No728NoNo128 + 642 MiBNo2??
Denver 2 [56] 2016ARMv8‑A?13Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW.		Direct+
Indirect branch
prediction		"Super" Nvidia's own implementation?16NoNo128 + 642 MiBNo2??
Carmel 2018ARMv8.2‑A?Direct+
Indirect branch
prediction		?12NoNo128 + 642 MiB(4 MiB @ 8 cores)2 (+ 8)??
Cavium ThunderX [57] [58] 2014ARMv8-A2-wide9 [58] Yes [57] Two-level?28NoNo78 + 32 [59] [60] 16 MiB [59] [60] No8–16, 24–48??
ThunderX2
[61] (ex. Broadcom Vulcan [62] )		2018 [63] ARMv8.1-A
[64] 		4-wide
"4 μops" [65] [66] 		?Yes [67] Multi-level??16 [68] SMT4No32 + 32
(data 8-way)		256 KiB
per core [69] 		1 MiB
per core [69] 		16–32 [69] ??
Marvell ThunderX3 2020 [70] ARMv8.3+ [70] 8-wide?Yes
4-wide dispatch		Multi-level?77 [70] SMT4 [70] ?64 + 32512 KiB
per core		90 MiB60??
Applied

Micro

Helix 2014???????40 / 28NoNo32 + 32 (per core;
write-through
w/parity) [71] 		256 KiB shared
per core pair (with ECC)		1 MiB/core2, 4, 8??
X-Gene 2013?4-wide15Yes???40 [72] NoNo8 MiB84.2?
X-Gene 22015?4-wide15Yes???28 [73] NoNo8 MiB84.2?
X-Gene 3 [73] 2017???????16NoNo??32 MiB32??
Qualcomm Kryo 2015ARMv8-A??YesTwo-level?"big" or "LITTLE"
Qualcomm's own similar implementation		?14 [74] NoNo32+24 [75] 0.5–1 MiB2+26.3?
Kryo 200 2016ARMv8-A2-wide11–12Yes
7-wide dispatch		Two-levelbig714 / 11 / 10 / 6 [76] NoNo64 + 32/64?512 KiB/Gold CoreNo4?1.8–2.45 GHz
2-wide8No0Conditional+
Indirect branch
prediction		LITTLE28–64? + 8–64?256 KiB/Silver Core4?1.8–1.9 GHz
Kryo 300 2017ARMv8.2-A3-wide11–13Yes
8-wide dispatch		Two-levelbig810 [76] NoNo64+64 [76] 256 KiB/Gold Core2 MiB2, 4?2.0–2.95 GHz
2-wide8No0Conditional+
Indirect branch
prediction		LITTLE2816–64? + 16–64?128 KiB/Silver4, 6?1.7–1.8 GHz
Kryo 400 2018ARMv8.2-A4-wide11–13Yes
8-wide dispatch		Yesbig811 / 8 / 7NoNo64 + 64512 KiB/Gold Prime

256 KiB/Gold

2 MiB2, 1+1, 4, 1+3?2.0–2.96 GHz
2-wide8No0Conditional+
Indirect branch
prediction		LITTLE216–64? + 16–64?128 KiB/Silver4, 6?1.7–1.8 GHz
Kryo 500 2019ARMv8.2-A4-wide11–13Yes
8-wide dispatch		Yesbig8 / 7No?512 KiB/Gold Prime

256 KiB/Gold

3 MiB2, 1+3?2.0–3.2 GHz
2-wide8No0Conditional+
Indirect branch
prediction		LITTLE2?128 KiB/Silver4, 6?1.7–1.8 GHz
Kryo 600 2020ARMv8.4-A4-wide11–13Yes
8-wide dispatch		Yesbig6 / 5No?64 + 641024 KiB/Gold Prime

512 KiB/Gold

4 MiB2, 1+3?2.2–3.0 GHz
2-wide8No0Conditional+
Indirect branch
prediction		LITTLE2?128 KiB/Silver4, 6?1.7–1.8 GHz
Falkor [77] [78] 2017 [79] "ARMv8.1-A features"; [78] AArch64  only (not 32-bit) [78] 4-wide10–15Yes
8-wide dispatch		Yes?810No24 KiB88 [78] + 32500KiB1.25MiB40–48??
Samsung M1 [80] [81] 2016ARMv8-A4-wide13 [82] Yes
9-wide dispatch [83] 		96big814NoNo64 + 322 MiB [84] No4?2.6 GHz
M2 [80] [81] 2017ARMv8-A4-wide100Two-levelbig10NoNo64 + 642 MiBNo4?2.3 GHz
M3 [82] [85] 2018ARMv8.2-A6-wide15Yes
12-wide dispatch		228Two-levelbig1210NoNo64 + 64512 KiB per core4096KB4?2.7 GHz
M4 [86] 2019ARMv8.2-A6-wide15Yes
12-wide dispatch		228Two-levelbig128 / 7NoNo64 + 64512 KiB per core3072KB2?2.73 GHz
M5 [87] 2020ARMv8.2-A6-wideYes
12-wide dispatch		228Two-levelbig7NoNo64 + 64512 KiB per core3072KB2?2.73 GHz
Fujitsu A64FX [88] [89] 2019ARMv8.2-A4/2-wide7+Yes
5-way?		Yesn/a8+2*512b [90] 7NoNo64 + 648MiB per 12+1 coresNo48+4?1.9 GHz+
HiSilicon TaiShan V110 [91] 2019ARMv8.2-A4-wide?Yesn/a87NoNo64 + 64512 KiB per core1 MiB per core???
CompanyCoreReleasedRevisionDecode Pipeline
depth		 Out-of-order
execution 		Branch
prediction 		big.LITTLE roleExec.
ports		 SIMD Fab
(in nm)		 Simult. MT L0 cache L1 cache
Instr  +  Data
(in KiB)		L2 cacheL3 cacheCore
configu-
rations		Speed per core (DMIPS/
MHz [note 1] )		 Clock rate ARM part number (in the main ID register)

See also

Notes

  1. 1 2 As Dhrystone (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads – use with caution.

Related Research Articles

ARM is a family of RISC instruction set architectures (ISAs) for computer processors. Arm Ltd. develops the ISAs and licenses them to other companies, who build the physical devices that use the instruction set. It also designs and licenses cores that implement these ISAs.

Adreno is a series of graphics processing unit (GPU) semiconductor intellectual property cores developed by Qualcomm and used in many of their SoCs.

<span class="mw-page-title-main">Qualcomm Snapdragon</span> Suite of system-on-a-chip (SoC) semiconductor products

Snapdragon is a suite of system on a chip (SoC) semiconductor products for mobile devices designed and marketed by Qualcomm Technologies Inc. The Snapdragon's central processing unit (CPU) uses the ARM architecture. As such, Qualcomm often refers to the Snapdragon as a "mobile platform". Snapdragon semiconductors are embedded in devices of various systems, including vehicles, Android, Windows Phone and netbooks. In addition to the processors, the Snapdragon line includes modems, Wi-Fi chips and mobile charging products.

<span class="mw-page-title-main">Apple silicon</span> System-on-chip processors designed by Apple Inc.

Apple silicon refers to a series of system on a chip (SoC) and system in a package (SiP) processors designed by Apple Inc., mainly using the ARM architecture. They are the basis of Mac, iPhone, iPad, Apple TV, Apple Watch, AirPods, AirTag, HomePod, and Apple Vision Pro devices.

<span class="mw-page-title-main">Exynos</span> Family of ARM based system-on-a-chip models

Exynos, formerly Hummingbird (Korean: 엑시노스), is a series of ARM-based system-on-chips developed by Samsung Electronics' System LSI division and manufactured by Samsung Foundry. It is a continuation of Samsung's earlier S3C, S5L and S5P line of SoCs.

<span class="mw-page-title-main">AArch64</span> 64-bit extension of the ARM architecture

AArch64 or ARM64 is the 64-bit extension of the ARM architecture family.

Qualcomm Kryo is a series of custom or semi-custom ARM-based CPUs included in the Snapdragon line of SoCs.

The ARM Cortex-A73 is a central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Sophia design centre. The Cortex-A73 is a 2-wide decode out-of-order superscalar pipeline. The Cortex-A73 serves as the successor of the Cortex-A72, designed to offer 30% greater performance or 30% increased power efficiency.

The ARM Cortex-A55 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre. The Cortex-A55 is a 2-wide decode in-order superscalar pipeline.

The ARM Cortex-A75 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings's Sophia design centre. The Cortex-A75 is a 3-wide decode out-of-order superscalar pipeline. The Cortex-A75 serves as the successor of the Cortex-A73, designed to improve performance by 20% over the A73 in mobile applications while maintaining the same efficiency.

The ARM Cortex-A76 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre. ARM states a 25% and 35% increase in integer and floating point performance, respectively, over a Cortex-A75 of the previous generation.

The ARM Cortex-A77 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre. ARM announced an increase of 23% and 35% in integer and floating point performance, respectively. Memory bandwidth increased 15% relative to the A76.

<span class="mw-page-title-main">Apple A13</span> System on a chip (SoC) designed by Apple Inc.

The Apple A13 Bionic is a 64-bit ARM-based system on a chip (SoC), designed by Apple Inc. It appears in the iPhone 11, 11 Pro/Pro Max, the 9th generation iPad, the iPhone SE and the Studio Display. Apple states that the two high performance cores are 20% faster with 30% lower power consumption than the Apple A12's, and the four high efficiency cores are 20% faster with 40% lower power consumption than the A12's.

The ARM Cortex-A78 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Ltd.'s Austin centre.

The ARM Cortex-X1 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre as part of ARM's Cortex-X Custom (CXC) program.

The ARM Cortex-A710 is the successor to the ARM Cortex-A78, being the First-Generation Armv9 “big” Cortex CPU. It is the companion to the ARM Cortex-A510 "LITTLE" efficiency core. It was designed by ARM Ltd.'s Austin centre. It is the fourth and last iteration of Arm’s Austin core family. It forms part of Arm's Total Compute Solutions 2021 (TCS21) along with Arm's Cortex-X2, Cortex-A510, Mali-G710 and CoreLink CI-700/NI-700.

The ARM Cortex-A510 is the successor to the ARM Cortex-A55 and the first ARMv9 high efficiency "LITTLE" CPU. It is the companion to the ARM Cortex-A710 "big" core. It is a clean-sheet 64-bit CPU designed by ARM Holdings' Cambridge design team.

The ARM Cortex-X2 is a central processing unit implementing the ARMv9-A 64-bit instruction set designed by ARM Holdings' Austin design centre as part of ARM's Cortex-X Custom (CXC) program.It forms part of Arm's Total Compute Solutions 2021 (TCS21) along with Arm's Cortex-A710, Cortex-A510, Mali-G710 and CoreLink CI-700/NI-700.

References

  1. ↑ "ARM V7 Differences". infocenter.arm.com. ARM Information Center. Retrieved 1 June 2016.
  2. 1 2 "ARM processor hardware virtualization support". arm.com. ARM Holdings . Retrieved 1 June 2016.
  3. 1 2 "big.LITTLE processing with ARM Cortex-A15 & Cortex-A7" (PDF). arm.com. ARM Holdings. Archived from the original (PDF) on 17 October 2013. Retrieved 6 August 2014.
  4. ↑ "Cortex-A7 processor". arm.com. ARM Holdings . Retrieved 1 June 2016.
  5. ↑ "Cortex-A8 architecture". processors.wiki.TI.com. Texas Instruments. Archived from the original on 8 August 2014. Retrieved 6 August 2014.
  6. ↑ "The ARM Cortex-A9 processors" (PDF). arm.com. ARM Holdings. Archived from the original (PDF) on 17 November 2014. Retrieved 6 August 2014.
  7. 1 2 "Cortex-A9 processor". arm.com. ARM Holdings . Retrieved 15 September 2014.
  8. ↑ "ARM Cortex-A17 / Cortex-A12 processor update – Architectures and Processors blog – Arm Community blogs – Arm Community".
  9. ↑ "Cortex-A15 processor". arm.com. ARM Holdings . Retrieved 9 August 2016.
  10. ↑ "ARM Cortex-A17 MPCore processor technical reference manual" (PDF). infocenter.arm.com. ARM Holdings . Retrieved 18 September 2014.
  11. ↑ Klug, Brian (7 October 2011). "Qualcomm's new Snapdragon S4: MSM8960 & Krait architecture explored". anandtech.com. Anandtech . Retrieved 6 August 2014.
  12. ↑ Mallia, Lou (2007). "Qualcomm High Performance Processor Core and Platform for Mobile Applications" (PDF). Archived from the original (PDF) on 26 April 2017. Retrieved 8 May 2014.
  13. ↑ "Qualcomm's New Snapdragon S4: MSM8960 & Krait Architecture Explored".
  14. ↑ "Qualcomm Snapdragon S4 (Krait) Performance Preview – 1.5 GHZ MSM8960 MDP and Adreno 225 Benchmarks".
  15. ↑ Frumusanu, Andrei (22 February 2016). "ARM Announces Cortex-A32 IoT and Embedded Processor". Anandtech.com. Retrieved 13 June 2016.
  16. ↑ "New Ultra-efficient ARM Cortex-A32 Processor Expands… – ARM". arm.com. Retrieved 1 October 2016.
  17. ↑ Ltd, Arm. "Cortex-A34". ARM Developer. Retrieved 10 October 2019.
  18. ↑ "Cortex-A35 Processor". ARM. ARM Ltd.
  19. ↑ Frumusanu, Andrei. "ARM Announces New Cortex-A35 CPU – Ultra-High Efficiency For Wearables & More".
  20. ↑ "Cortex-A53 Processor". ARM. ARM Ltd.
  21. 1 2 Matt, Humrick (29 May 2017). "Exploring DynamIQ and ARM's New CPUs: Cortex-A75, Cortex-A55". Anandtech.com. Retrieved 29 May 2017.
  22. ↑ "Qualcomm Snapdragon 888 5G Mobile Platform" . Retrieved 6 January 2021.
  23. ↑ Based on 18% perf. increment over Cortex-A53 "Arm Cortex-A55: Efficient performance from edge to cloud". ARM. ARM Ltd.
  24. ↑ Smith, Andrei Frumusanu, Ryan. "ARM A53/A57/T760 investigated – Samsung Galaxy Note 4 Exynos Review". anandtech.com. Retrieved 17 June 2019.{{cite web}}: CS1 maint: multiple names: authors list (link)
  25. ↑ "TSMC Delivers First Fully Functional 16FinFET Networking Processor" (Press release). TSMC. 25 September 2014. Archived from the original on 20 February 2015. Retrieved 19 February 2015.
  26. ↑ "Cortex-A65 – Arm Developer". ARM Ltd. Retrieved 14 July 2020.
  27. ↑ "Cortex-A65AE – Arm Developer". ARM Ltd. Retrieved 26 April 2019.
  28. ↑ Frumusanu, Andrei. "ARM Reveals Cortex-A72 Architecture Details". Anandtech. Retrieved 25 April 2015.
  29. 1 2 3 4 "ARM's processor lines" (PDF). users.nik.uni-obuda.hu. November 2018. Retrieved 24 October 2023.
  30. ↑ Frumusanu, Andrei (29 May 2016). "The ARM Cortex A73 – Artemis Unveiled". Anandtech.com. Retrieved 31 May 2016.
  31. ↑ Frumusanu, Andrei (31 May 2018). "ARM Cortex-A76 CPU Unveiled". Anandtech. Retrieved 1 June 2018.
  32. ↑ "Cortex-A76AE – Arm Developer". ARM Ltd. Retrieved 14 July 2020.
  33. ↑ Schor, David (26 May 2019). "Arm Unveils Cortex-A77, Emphasizes Single-Thread Performance". WikiChip Fuse. Retrieved 17 June 2019.
  34. ↑ According to ARM, the Cortex-A77 has a 20% IPC single-thread performance improvement over its predecessor in Geekbench 4, 23% in SPECint2006, 35% in SPECfp2006, 20% in SPECint2017, and 25% in SPECfp2017
  35. ↑ "Arm Unveils the Cortex-A78: When Less Is More". WikiChip Fuse. 26 May 2020. Retrieved 28 May 2020.
  36. ↑ Ltd, Arm. "Cortex-A78". ARM Developer. Retrieved 28 May 2020.
  37. 1 2 3 4 5 "Introducing the Arm Cortex-X Custom program". community.arm.com. Retrieved 28 May 2020.
  38. ↑ Lal Shimpi, Anand (17 September 2013). "The iPhone 5s Review: The Move to 64-bit". AnandTech. Retrieved 3 July 2014.
  39. 1 2 3 4 5 6 7 8 9 Lal Shimpi, Anand (31 March 2014). "Apple's Cyclone Microarchitecture Detailed". AnandTech. Retrieved 3 July 2014.
  40. ↑ Dixon-Warren, Sinjin (20 January 2014). "Samsung 28nm HKMG Inside the Apple A7". Chipworks. Archived from the original on 6 April 2014. Retrieved 3 July 2014.
  41. ↑ Lal Shimpi, Anand (17 September 2013). "The iPhone 5s Review: A7 SoC Explained". AnandTech. Retrieved 3 July 2014.
  42. 1 2 3 4 5 6 7 8 9 10 Ho, Joshua; Smith, Ryan (2 November 2015). "The Apple iPhone 6s and iPhone 6s Plus Review". AnandTech. Retrieved 13 February 2016.
  43. ↑ "Apple had shifted the microarchitecture in Hurricane (A10) from a 6-wide decode from to a 7-wide decode". AnandTech. 5 October 2018.
  44. 1 2 3 4 "Apple A10 Fusion". system-on-a-chip.specout.com. Retrieved 1 October 2016.[ permanent dead link ]
  45. 1 2 3 4 5 "Measured and Estimated Cache Sizes". AnandTech. 5 October 2018.
  46. 1 2 "Apple A11 New Instruction Set Extensions" (PDF). Apple Inc. 8 June 2018.
  47. 1 2 "Apple A12 Pointer Authentication Codes". Jonathan Levin, @Morpheus. 12 September 2018. Archived from the original on 10 October 2018. Retrieved 8 October 2018.
  48. 1 2 "A13 has ARMv8.4, apparently (LLVM project sources, thanks, @Longhorn)". Jonathan Levin, @Morpheus. 13 March 2020.
  49. ↑ "The Apple A13 SoC: Lightning & Thunder". AnandTech. 16 October 2019.
  50. ↑ "The A13's Memory Subsystem: Faster L2, More SLC BW". AnandTech. 16 October 2019.
  51. 1 2 3 4 5 6 "llvm-project/llvm/lib/Target/AArch64/AArch64.td at main - llvm/llvm-project - GitHub". github.com. Retrieved 3 July 2023.
  52. ↑ "Apple Announces The Apple Silicon M1: Ditching x86 – What to Expect, Based on A14". AnandTech. 10 November 2020.
  53. ↑ Frumusanu, Andrei. "Apple Announces The Apple Silicon M1: Ditching x86 – What to Expect, Based on A14". anandtech.com. Retrieved 25 November 2020.
  54. ↑ Stam, Nick (11 August 2014). "Mile High Milestone: Tegra K1 "Denver" Will Be First 64-bit ARM Processor for Android". NVidia. Archived from the original on 12 August 2014. Retrieved 11 August 2014.
  55. ↑ Gwennap, Linley. "Denver Uses Dynamic Translation to Outperform Mobile Rivals". The Linley Group. Retrieved 24 April 2015.
  56. ↑ Ho, Joshua (25 August 2016). "Hot Chips 2016: NVIDIA Discloses Tegra Parker Details". Anandtech. Retrieved 25 August 2016.
  57. 1 2 De Gelas, Johan (16 December 2014). "ARM Challenging Intel in the Server Market". Anandtech. Retrieved 8 March 2017.
  58. 1 2 De Gelas, Johan (15 June 2016). "Investigating the Cavium ThunderX". Anandtech. Retrieved 8 March 2017.
  59. 1 2 "64-bit Cortex Platform To Take on x86 Servers in the Cloud". electronic design. 5 June 2014. Retrieved 7 February 2015.
  60. 1 2 "ThunderX_CP™ Family of Workload Optimized Compute Processors" (PDF). Cavium. 2014. Retrieved 7 February 2015.
  61. ↑ "A Look at Cavium's New High-Performance ARM Microprocessors and the Isambard Supercomputer". WikiChip Fuse. 3 June 2018. Retrieved 17 June 2019.
  62. ↑ "⚙ D30510 Vulcan is now ThunderX2T99". reviews.llvm.org.
  63. ↑ Kennedy, Patrick (7 May 2018). "Cavium ThunderX2 256 Thread Arm Platforms Hit General Availability" . Retrieved 10 May 2018.
  64. ↑ "⚙ D21500 [AARCH64] Add support for Broadcom Vulcan". reviews.llvm.org.
  65. ↑ Hayes, Eric (7 April 2014). "IDC HPC USER FORUM" (PDF). hpcuserforum.com.
  66. ↑ "The Linley Group – Processor Conference 2013". linleygroup.com.
  67. ↑ "ThunderX2 ARM Processors- A Game Changing Family of Workload Optimized Processors for Data Center and Cloud Applications – Cavium". cavium.com.
  68. ↑ "Broadcom Announces Server-Class ARMv8-A Multi-Core Processor Architecture". Broadcom. 15 October 2013. Retrieved 11 August 2014.
  69. 1 2 3 Kennedy, Patrick (9 May 2018). "Cavium ThunderX2 Review and Benchmarks a Real Arm Server Option". Serve the Home. Retrieved 10 May 2018.
  70. 1 2 3 4 Frumusanu, Andrei (16 March 2020). "Marvell Announces ThunderX3: 96 Cores & 384 Thread 3rd Gen Arm Server Processor".
  71. ↑ Ganesh T S (3 October 2014). "ARMv8 Goes Embedded with Applied Micro's HeliX SoCs". AnandTech. Retrieved 9 October 2014.
  72. ↑ Morgan, Timothy Prickett (12 August 2014). "Applied Micro Plots Out X-Gene ARM Server Future". Enterprisetech. Retrieved 9 October 2014.
  73. 1 2 De Gelas, Johan (15 March 2017). "AppliedMicro's X-Gene 3 SoC Begins Sampling". Anandtech. Retrieved 15 March 2017.
  74. ↑ "Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute". Qualcomm. 2 September 2015. Retrieved 6 September 2015.
  75. ↑ Frumusanu, Ryan Smith, Andrei. "The Qualcomm Snapdragon 820 Performance Preview: Meet Kryo".{{cite web}}: CS1 maint: multiple names: authors list (link)
  76. 1 2 3 Smith, Andrei Frumusanu, Ryan. "The Snapdragon 845 Performance Preview: Setting the Stage for Flagship Android 2018" . Retrieved 11 June 2018.{{cite news}}: CS1 maint: multiple names: authors list (link)
  77. ↑ Shilov, Anton (16 December 2016). "Qualcomm Demos 48-Core Centriq 2400 SoC in Action, Begins Sampling". Anandtech. Retrieved 8 March 2017. In 2015, Qualcomm teamed up with Xilinx and Mellanox to ensure that its server SoCs are compatible with FPGA-based accelerators and data-center connectivity solutions (the fruits of this partnership will likely emerge in 2018 at best).
  78. 1 2 3 4 Cutress, Ian (20 August 2017). "Analyzing Falkor's Microarchitecture". Anandtech. Retrieved 21 August 2017. The CPU cores, code named Falkor, will be ARMv8.0 compliant although with ARMv8.1 features, allowing software to potentially seamlessly transition from other ARM environments (or need a recompile). The Centriq 2400 family is set to be AArch64 only, without support for AArch32: Qualcomm states that this saves some power and die area, but that they primarily chose this route because the ecosystems they are targeting have already migrated to 64-bit. Qualcomm's Chris Bergen, Senior Director of Product Management for the Centriq 2400, stated that the majority of new and upcoming companies have started off with 64-bit as their base in the data center, and not even considering 32-bit, which is a reason for the AArch64-only choice here. [..] Micro-op cache / L0 I-cache with Way prediction [..] The L1 I-cache is 64KB, which is similar to other ARM architecture core designs, and also uses 64-byte lines but with an 8-way associativity. To software, as the L0 is transparent, the L1 I-cache will show as an 88KB cache.
  79. ↑ Shrout, Ryan (8 November 2017). "Qualcomm Centriq 2400 Arm-based Server Processor Begins Commercial Shipment". PC Per. Retrieved 8 November 2017.
  80. 1 2 Ho, Joshua. "Hot Chips 2016: Exynos M1 Architecture Disclosed".
  81. 1 2 Frumusanu, Andrei. "Samsung Announces Exynos 8890 with Cat.12/13 Modem and Custom CPU".
  82. 1 2 Frumusanu, Andrei (23 January 2018). "The Samsung Exynos M3 – 6-wide Decode with 50%+ IPC Increase". Anandtech. Retrieved 25 January 2018.
  83. ↑ Frumusanu, Andrei. "Hot Chips 2016: Exynos M1 Architecture Disclosed". Anandtech. Retrieved 29 May 2017.
  84. ↑ "'Neural network' spotted deep inside Samsung's Galaxy S7 silicon brain". The Register .
  85. ↑ Frumusanu, Andrei. "Hot Chips 2018: Samsung's Exynos-M3 CPU Architecture Deep Dive". anandtech.com. Retrieved 17 June 2019.
  86. ↑ Schor, David (14 January 2019). "Samsung Discloses Exynos M4 Changes, Upgrades Support for ARMv8.2, Rearranges The Back-End". WikiChip Fuse. Retrieved 17 June 2019.
  87. ↑ Frumusanu, Andrei. "ISCA 2020: Evolution of the Samsung Exynos CPU Microarchitecture". anandtech.com. Retrieved 24 January 2021.
  88. ↑ Fujitsu High Performance CPU for the Post-K Computer (PDF), 21 July 2018, retrieved 16 September 2019
  89. ↑ Arm A64fx and Post-K: Game Changing CPU & Supercomputer for HPC and its Convergence of with Big Data / AI (PDF), 3 April 2019, retrieved 16 September 2019
  90. ↑ "Fujitsu Successfully Triples the Power Output of Gallium-Nitride Transistors – Fujitsu Global". fujitsu.com. Retrieved 23 November 2020.
  91. ↑ Schor, David (3 May 2019). "Huawei Expands Kunpeng Server CPUs, Plans SMT, SVE For Next Gen". WikiChip Fuse. Retrieved 13 December 2019.
This page is based on this Wikipedia article
Text is available under the CC BY-SA 4.0 license; additional terms may apply.
Images, videos and audio are available under their respective licenses.