Penryn (microarchitecture)

Last updated
Penryn
General information
LaunchedNovember 2007;16 years ago (November 2007)
Performance
Max. CPU clock rate 1.06 GHz to 3.33 GHz
FSB speeds533 MT/s to 1600 MT/s
Cache
L1 cache 64 KB per core
L2 cache1 MB to 12 MB unified
L3 cache8 MB to 16 MB shared (Xeon)
Architecture and classification
Microarchitecture Core
Instruction set x86-16, IA-32, x86-64
Extensions
Physical specifications
Transistors
Cores
  • 1-4 (2-6 Xeon)
Socket(s)
Products, models, variants
Model(s)
  • P6 Family (Celeron, Pentium, Pentium Dual-Core, Core 2 range, Xeon)
History
Predecessor(s) Core
Successor(s) Nehalem
Support status
Unsupported

In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket P), Wolfdale (LGA 775) and Yorkfield (MCM, LGA 775), some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the Wolfdale-DP and Harpertown code names are used for LGA 771 based MCMs with two or four active Wolfdale cores.

Contents

Architectural improvements over 65-nanometer Core 2 CPUs include a new divider with reduced latency, a new shuffle engine, and SSE4.1 instructions (some of which are enabled by the new single-cycle shuffle engine). [1]

Maximum L2 cache size per chip was increased from 4 to 6 MB, with L2 associativity increased from 16-way to 24-way. Cut-down versions with 3 MB L2 also exist, which are commonly called Penryn-3M and Wolfdale-3M as well as Yorkfield-6M, respectively. The single-core version of Penryn, listed as Penryn-L here, is not a separate model like Merom-L but a version of the Penryn-3M model with only one active core.

CPU List

ProcessorBrand nameModel (list)CoresL2 CacheSocket TDP
Penryn-L Core 2 Solo SU3xxx 13  MB BGA9565.5  W
Penryn-3M Core 2 Duo SU7xxx 23 MBBGA95610 W
SU9xxx
Penryn SL9xxx 6 MB17 W
SP9xxx 25/28 W
Penryn-3M P7xxx 3 MB Socket P
FCBGA6
25 W
P8xxx
Penryn P9xxx 6 MB
Penryn-3M T6xxx 2 MB35 W
T8xxx 3 MB
Penryn T9xxx 6 MB
E8x35 6 MBSocket P35-55 W
Penryn-QCCore 2 Quad Q9xxx 42x3-2x6 MBSocket P45 W
Penryn XECore 2 Extreme X9xxx 26 MBSocket P44 W
Penryn-QC QX9xxx 42x6 MB45 W
Penryn-3M Celeron T3xxx 21 MBSocket P35 W
SU2xxx µFC-BGA 95610 W
Penryn-L 9x0 11 MBSocket P35 W
7x3 µFC-BGA 95610 W
Penryn-3M Pentium T4xxx 21 MBSocket P35 W
SU4xxx 2 MBµFC-BGA 95610 W
Penryn-L SU2xxx 15.5 W
Wolfdale-3M
Celeron E3xxx 21 MBLGA 77565 W
Pentium E2210
E5xxx 2 MB
E6xxx
Core 2 Duo E7xxx 3 MB
Wolfdale E8xxx 6 MB
Xeon 31x0 45-65 W
Wolfdale-CL 30x4 1 LGA 771 30 W
31x3 265 W
Yorkfield Xeon X33x0 42×3–2×6 MB LGA 775 65–95 W
Yorkfield-CL X33x3 LGA 771 80 W
Yorkfield-6M Core 2 Quad Q8xxx 2×2 MBLGA 77565–95 W
Q9x0x 2×3 MB
Yorkfield Q9x5x 2×6 MB
Yorkfield XECore 2 Extreme QX9xxx 2×6 MB130–136 W
QX9xx5 LGA 771150 W
Wolfdale-DP Xeon E52xx 26 MBLGA 77165 W
L52xx20-55 W
X52xx80 W
Harpertown E54xx 42×6 MBLGA 77180 W
L54xx40-50 W
X54xx120-150 W

Processor cores

The processors of the Core microarchitecture can be categorized by number of cores, cache size, and socket; each combination of these has a unique code name and product code that is used across a number of brands. For instance, code name "Allendale" with product code 80557 has two cores, 2 MB L2 cache and uses the desktop socket 775, but has been marketed as Celeron, Pentium, Core 2 and Xeon, each with different sets of features enabled. Most of the mobile and desktop processors come in two variants that differ in the size of the L2 cache, but the specific amount of L2 cache in a product can also be reduced by disabling parts at production time. Wolfdale-DP and all quad-core processors except Dunnington QC are multi-chip modules combining two dies. For the 65 nm processors, the same product code can be shared by processors with different dies, but the specific information about which one is used can be derived from the stepping.

fabcoresMobileDesktop, UP ServerCL ServerDP ServerMP Server
Single-Core 45 nm 45 nm 1 Penryn-L
80585
Wolfdale-CL
80588
Dual-Core 45 nm45 nm2 Penryn-3M
80577
Penryn
80576
Wolfdale-3M
80571
Wolfdale
80570
Wolfdale-CL
80588
Wolfdale-DP
80573
Quad-Core 45 nm45 nm4 Penryn-QC
80581
Yorkfield-6M
80580
Yorkfield
80569
Yorkfield-CL
80584
Harpertown
80574
Dunnington QC
80583
Six-Core 45 nm45 nm6 Dunnington
80582

Steppings using 45 nm process

Mobile (Penryn)Desktop (Wolfdale)Desktop (Yorkfield)Server (Wolfdale-DP, Harpertown, Dunnington)
SteppingReleasedAreaCPUIDL2 cacheMax. clock Celeron Pentium Core 2 Celeron Pentium Core 2 Xeon Core 2 Xeon Xeon
C0Nov 2007107 mm2106766 MB3.00 GHz E8000 P7000 T8000 T9000 P9000 SP9000 SL9000 X9000 E8000 3100 QX9000 5200 5400
M0Mar 200882 mm2106763 MB2.40 GHz 7xx SU3000 P7000 P8000 T8000 SU9000 E5000 E2000 E7000
C1Mar 2008107 mm2106776 MB3.20 GHz Q9000 QX9000 3300
M1Mar 200882 mm2106773 MB2.50 GHz Q8000 Q9000 3300
E0Aug 2008107 mm21067A6 MB3.33 GHz T9000 P9000 SP9000 SL9000 Q9000 QX9000 E8000 3100 Q9000 Q9000S QX9000 3300 5200 5400
R0Aug 200882 mm21067A3 MB2.93 GHz 7xx 900 SU2000 T3000 T4000 SU2000 SU4000 SU3000 T6000 SU7000 P8000 SU9000 E3000 E5000 E6000 E7000 Q8000 Q8000S Q9000 Q9000S 3300
A1Sep 2008503 mm2106D13 MB2.67 GHz 7400

In the model 23 (cpuid 01067xh), Intel started marketing stepping with full (6 MB) and reduced (3 MB) L2 cache at the same time, and giving them identical cpuid values. All steppings have the new SSE4.1 instructions. Stepping C1/M1 was a bug fix version of C0/M0 specifically for quad core processors and only used in those. Stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and replaces all earlier steppings.

In mobile processors, stepping C0/M0 is only used in the Intel Mobile 965 Express (Santa Rosa refresh) platform, whereas stepping E0/R0 supports the later Intel Mobile 4 Express (Montevina) platform.

Model 29 stepping A1 (cpuid 106d1h) adds an L3 cache as well as six instead of the usual two cores, which leads to an unusually large die size of 503 mm2. [2] As of February 2008, it has only found its way into the very high-end Xeon 7400 series (Dunnington).

Roadmap

See also

Related Research Articles

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Celeron is a discontinued series of low-end IA-32 and x86-64 computer microprocessor models targeted at low-cost personal computers, manufactured by Intel. The first Celeron-branded CPU was introduced on April 15, 1998, and was based on the Pentium II.

<span class="mw-page-title-main">Pentium 4</span> Brand by Intel

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<span class="mw-page-title-main">Xeon</span> Line of Intel server and workstation processors

Xeon is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded markets. It was introduced in June 1998. Xeon processors are based on the same architecture as regular desktop-grade CPUs, but have advanced features such as support for error correction code (ECC) memory, higher core counts, more PCI Express lanes, support for larger amounts of RAM, larger cache memory and extra provision for enterprise-grade reliability, availability and serviceability (RAS) features responsible for handling hardware exceptions through the Machine Check Architecture (MCA). They are often capable of safely continuing execution where a normal processor cannot due to these extra RAS features, depending on the type and severity of the machine-check exception (MCE). Some also support multi-socket systems with two, four, or eight sockets through use of the Ultra Path Interconnect (UPI) bus, which replaced the older QuickPath Interconnect (QPI) bus.

<span class="mw-page-title-main">P6 (microarchitecture)</span> Intel processor microarchitecture

The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is frequently referred to as i686. It was planned to be succeeded by the NetBurst microarchitecture used by the Pentium 4 in 2000, but was revived for the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from P6.

The Intel Core microarchitecture is a multi-core processor microarchitecture launched by Intel in mid-2006. It is a major evolution over the Yonah, the previous iteration of the P6 microarchitecture series which started in 1995 with Pentium Pro. It also replaced the NetBurst microarchitecture, which suffered from high power consumption and heat intensity due to an inefficient pipeline designed for high clock rate. In early 2004 the new version of NetBurst (Prescott) needed very high power to reach the clocks it needed for competitive performance, making it unsuitable for the shift to dual/multi-core CPUs. On May 7, 2004 Intel confirmed the cancellation of the next NetBurst, Tejas and Jayhawk. Intel had been developing Merom, the 64-bit evolution of the Pentium M, since 2001, and decided to expand it to all market segments, replacing NetBurst in desktop computers and servers. It inherited from Pentium M the choice of a short and efficient pipeline, delivering superior performance despite not reaching the high clocks of NetBurst.

<span class="mw-page-title-main">Intel Core 2</span> Processor family by Intel

Intel Core 2 was a processor family encompassing a range of Intel's mainstream 64-bit x86-64 single-, dual-, and quad-core microprocessors based on the Core microarchitecture. The single- and dual-core models are single-die, whereas the quad-core models comprise two dies, each containing two cores, packaged in a multi-chip module. The Core 2 range was the last flagship range of Intel desktop processors to use a front-side bus (FSB).

<span class="mw-page-title-main">Pentium</span> Brand of discontinued microprocessors produced by Intel

Pentium is a discontinued series of x86 architecture-compatible microprocessors produced by Intel. The original Pentium was first released on March 22, 1993. The name "Pentium" is originally derived from the Greek word pente (πεντε), meaning "five", a reference to the prior numeric naming convention of Intel's 80x86 processors (8086–80486), with the Latin ending -ium since the processor would otherwise have been named 80586 using that convention.

<span class="mw-page-title-main">LGA 771</span>

LGA 771, also known as Socket J, is a CPU interface introduced by Intel in 2006. It is used in Intel Core microarchitecture and NetBurst microarchitecture (Dempsey) based DP-capable server processors, the Dual-Core Xeon is codenamed Dempsey, Woodcrest, and Wolfdale and the Quad-Core processors Clovertown, Harpertown, and Yorkfield-CL. It is also used for the Core 2 Extreme QX9775, and blade servers designated under Conroe-CL.

<span class="mw-page-title-main">Pentium Dual-Core</span> Line of CPUs by Intel

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<span class="mw-page-title-main">Conroe (microprocessor)</span> Code name for several Intel processors

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<span class="mw-page-title-main">Merom (microprocessor)</span> Code name for various mobile Intel processors

Merom is the code name for various mobile Intel processors that are sold as Core 2 Duo, Core 2 Solo, Pentium Dual-Core and Celeron. It was the first mobile processor to be based on the Core microarchitecture, replacing the Enhanced Pentium M-based Yonah processor. Merom has the product code 80537, which is shared with Merom-2M and Merom-L that are very similar but have a smaller L2 cache. Merom-L has only one processor core and a different CPUID model. The desktop version of Merom is Conroe and the dual-socket server version is Woodcrest. Merom was manufactured in a 65 nanometer process, and was succeeded by Penryn, a 45 nm version of the Merom architecture. Together, Penryn and Merom represented the first 'tick-tock' in Intel's Tick-Tock manufacturing paradigm, in which Penryn was the 'tick' to Merom's 'tock'.

<span class="mw-page-title-main">Penryn (microprocessor)</span> Mobile processor from Intel

Penryn is the code name of a mobile processor from Intel that is sold in varying configurations such as Core 2 Solo, Core 2 Duo, Core 2 Quad, Pentium and Celeron.

<span class="mw-page-title-main">Wolfdale (microprocessor)</span>

Wolfdale is the code name for a processor from Intel that is sold in varying configurations as Core 2 Duo, Celeron, Pentium and Xeon. In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was Penryn microarchitecture, the shrink of the Merom microarchitecture to 45 nanometers as CPUID model 23. This replaced the Conroe processor with Wolfdale.

<span class="mw-page-title-main">Yorkfield</span>

Yorkfield is the code name for some Intel processors sold as Core 2 Quad and Xeon. In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was Penryn microarchitecture, the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23, replacing Kentsfield, the previous model.

Lynnfield is the code name for a quad-core processor from Intel released in September 2009. It was sold in varying configurations as Core i5-7xx, Core i7-8xx or Xeon X34xx. Lynnfield uses the Nehalem microarchitecture and replaces the earlier Penryn based Wolfdale and Yorkfield processors, using the same 45 nm process technology, but with a new memory and bus interface. The product code for Lynnfield is 80605, its CPUID value identifies it as family 6, model 30 (0106Ex).

References

  1. "Intel Core 2 Extreme QX9650 - Penryn Ticks Ahead".
  2. "ARK entry for Intel Xeon Processor X7460". Intel. Retrieved 14 July 2009.