Comparison of instruction set architectures

An instruction set architecture (ISA) is an abstract model of a computer, also referred to as computer architecture. A realization of an ISA is called an implementation. An ISA permits multiple implementations that may vary in performance, physical size, and monetary cost (among other things); because the ISA serves as the interface between software and hardware. Software that has been written for an ISA can run on different implementations of the same ISA. This has enabled binary compatibility between different generations of computers to be easily achieved, and the development of computer families. Both of these developments have helped to lower the cost of computers and to increase their applicability. For these reasons, the ISA is one of the most important abstractions in computing today.

An ISA defines everything a machine language programmer needs to know in order to program a computer. What an ISA defines differs between ISAs; in general, ISAs define the supported data types, what state there is (such as the main memory and registers) and their semantics (such as the memory consistency and addressing modes), the instruction set (the set of machine instructions that comprises a computer's machine language), and the input/output model.

Data representation

In the early decades of computing, there were computers that used binary, decimal ^[1] and even ternary. ^{[2] [3]} Contemporary computers are almost exclusively binary.

Characters are encoded as strings of bits or digits, using a wide variety of character sets; even within a single manufacturer there were character set differences.

Integers are encoded with a variety of representations, including Sign_magnitude, Ones' complement, Two's complement, Offset binary, Nines' complement and Ten's complement.

Similarly, floating point numbers are encoded with a variety of representations for the sign, exponent and mantissa. In contemporary machines IBM hexadecimal floating-point and IEEE 754 floating point have largely supplanted older formats.

Addresses are typically unsigned integers generated from a combination of fields in an instruction, data from registers and data from storage; the details vary depending on the architecture.

Bits

Computer architectures are often described as n-bit architectures. In the first 3⁄4 of the 20th century, n is often 12, 18, 24, 30, 36, 48 or 60. In the last 1⁄3 of the 20th century, n is often 8, 16, or 32, and in the 21st century, n is often 16, 32 or 64, but other sizes have been used (including 6, 39, 128). This is actually a simplification as computer architecture often has a few more or less "natural" data sizes in the instruction set, but the hardware implementation of these may be very different. Many instruction set architectures have instructions that, on some implementations of that instruction set architecture, operate on half and/or twice the size of the processor's major internal datapaths. Examples of this are the Z80, MC68000, and the IBM System/360. On these types of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a 32-bit architecture with a 16-bit implementation. The IBM System/360 instruction set architecture is 32-bit, but several models of the System/360 series, such as the IBM System/360 Model 30, have smaller internal data paths, while others, such as the 360/195, have larger internal data paths. The external databus width is not used to determine the width of the architecture; the NS32008, NS32016 and NS32032 were basically the same 32-bit chip with different external data buses; the NS32764 had a 64-bit bus, and used 32-bit register. Early 32-bit microprocessors often had a 24-bit address, as did the System/360 processors.

Digits

In the first 3⁄4 of the 20th century, word oriented decimal computers typically had 10 digit ^{[4] [5] [6]} words with a separate sign, using all ten digits in integers and using two digits for exponents ^{[7] [5]} in floating point numbers.

Endianness

An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little-endian processors order bytes in memory with the least significant byte of a multi-byte value in the lowest-numbered memory location. Big-endian architectures instead arrange bytes with the most significant byte at the lowest-numbered address. The x86 architecture as well as several 8-bit architectures are little-endian. Most RISC architectures (SPARC, Power, PowerPC, MIPS) were originally big-endian (ARM was little-endian), but many (including ARM) are now configurable as either.

Endianness only applies to processors that allow individual addressing of units of data (such as bytes) that are smaller than some of the data formats.

Instruction formats

Opcodes

In some architectures, an instruction has a single opcode. In others, some instructions have an opcode and one or more modifiers. E.g., on the IBM System/370, byte 0 is the opcode but when byte 0 is a B2₁₆ then byte 1 selects a specific instruction, e.g., B205₁₆ is store clock (STCK).

Operands

Addressing modes

Architectures typically allow instructions to include some combination of operand addressing modes

Direct

The instruction specifies a complete (virtual) address

Immediate

The instruction specifies a value rather than an address

Indexed

The instruction specifies a register to use as an index. In some architecture the index is scaled by the operand length.

Indirect

The instruction specifies the location of a word that describes the operand, possibly involving multiple levels of indexing and indirection.

Truncated

Base-displacement

The instruction specifies a displacement from an address in a register

autoincrement/aurodecrement

A register used for indexing is incremented or decremented by 1, an operand size or an explicit delta

Number of operands

Main article: instruction set § Number of operands

The number of operands is one of the factors that may give an indication about the performance of the instruction set. A three-operand architecture (2-in, 1-out) will allow

A := B + C

to be computed in one instruction

ADD B, C, A

A two-operand architecture (1-in, 1-in-and-out) will allow

A := A + B

to be computed in one instruction

ADD B, A

but requires that

A := B + C

be done in two instructions

MOVE B, A ADD C, A

Encoding length

As can be seen in the table below some instructions sets keep to a very simple fixed encoding length, and other have variable-length. Usually it is RISC architectures that have fixed encoding length and CISC architectures that have variable length, but not always.

Instruction sets

The table below compares basic information about instruction set architectures.

Notes:

• Usually the number of registers is a power of two, e.g. 8, 16, 32. In some cases a hardwired-to-zero pseudo-register is included, as "part" of register files of architectures, mostly to simplify indexing modes. The column "Registers" only counts the integer "registers" usable by general instructions at any moment. Architectures always include special-purpose registers such as the program counter (PC). Those are not counted unless mentioned. Note that some architectures, such as SPARC, have register windows; for those architectures, the count indicates how many registers are available within a register window. Also, non-architected registers for register renaming are not counted.
• In the "Type" column, "Register–Register" is a synonym for a common type of architecture, "load–store", meaning that no instruction can directly access memory except some special ones, i.e. load to or store from register(s), with the possible exceptions of memory locking instructions for atomic operations.
• In the "Endianness" column, "Bi" means that the endianness is configurable.

Archi- tecture	Bits	Version	Intro- duced	Max # operands	Type	Design	Registers (excluding FP/vector)	Instruction encoding	Branch evaluation	Endian- ness	Extensions	Open	Royalty free
6502	8		1975	1	Register–Memory	CISC	3	Variable (8- to 24-bit)	Condition register	Little
6800	8		1974	1	Register–Memory	CISC	3	Variable (8- to 24-bit)	Condition register	Big
6809	8		1978	1	Register–Memory	CISC	5	Variable (8- to 32-bit)	Condition register	Big
680x0	32		1979	2	Register–Memory	CISC	8 data and 8 address	Variable	Condition register	Big
8080	8		1974	2	Register–Memory	CISC	7	Variable (8 to 24 bits)	Condition register	Little
8051	32 (8→32)		1977?	1	Register–Register	CISC	32 in 4-bit 16 in 8-bit 8 in 16-bit 4 in 32-bit	Variable (8 to 24 bits)	Compare and branch	Little
x86	16, 32, 64 (16→32→64)		1978	2 (integer) 3 (AVX) [lower-alpha 1] 4 (FMA4 and VPBLENDVPx) [8]	Register–Memory	CISC	8 (+ 4 or 6 segment reg.) (16/32-bit) 16 (+ 2 segment reg. gs/cs) (64-bit) 32 with AVX-512	Variable(8086 ~ 80386: variable between 1 and 6 bytes /w MMU + intel SDK, 80486: 2 to 5 bytes with prefix, pentium and onward: 2 to 4 bytes with prefix, x64: 4 bytes prefix, third party x86 emulation: 1 to 15 bytes w/o prefix & MMU . SSE/MMX: 4 bytes /w prefix AVX: 8 Bytes /w prefix)	Condition code	Little	x87, IA-32, MMX, 3DNow!, SSE, SSE2, PAE, x86-64, SSE3, SSSE3, SSE4, BMI, AVX, AES, FMA, XOP, F16C	No	No
Alpha	64		1992	3	Register–Register	RISC	32 (including "zero")	Fixed (32-bit)	Condition register	Bi	MVI, BWX, FIX, CIX	No
ARC	16/32/64 (32→64)	ARCv3 [9]	1996	3	Register–Register	RISC	16 or 32 including SP user can increase to 60	Variable (16- or 32-bit)	Compare and branch	Bi	APEX User-defined instructions
ARM/A32	32	ARMv1–v9	1983	3	Register–Register	RISC	15	Fixed (32-bit)	Condition code	Bi	NEON, Jazelle, VFP, TrustZone, LPAE		No
Thumb/T32	32	ARMv4T-ARMv8	1994	3	Register–Register	RISC	7 with 16-bit Thumb instructions 15 with 32-bit Thumb-2 instructions	Thumb: Fixed (16-bit), Thumb-2: Variable (16- or 32-bit)	Condition code	Bi	NEON, Jazelle, VFP, TrustZone, LPAE		No
Arm64/A64	64	ARMv8-A [10]	2011 [11]	3	Register–Register	RISC	32 (including the stack pointer/"zero" register)	Fixed (32-bit), Variable (32-bit or 64-bit for FMA4 with 32-bit prefix [12] )	Condition code	Bi	SVE and SVE2		No
AVR	8		1997	2	Register–Register	RISC	32 16 on "reduced architecture"	Variable (mostly 16-bit, four instructions are 32-bit)	Condition register, skip conditioned on an I/O or general purpose register bit, compare and skip	Little
AVR32	32	Rev 2	2006	2–3		RISC	15	Variable [13]		Big	Java virtual machine
Blackfin	32		2000	3 [14]	Register–Register	RISC [15]	2 accumulators 8 data registers 8 pointer registers 4 index registers 4 buffer registers	Variable (16- or 32-bit)	Condition code	Little [16]
CDC Upper 3000 series	48		1963	3	Register–Memory	CISC	48-bit A reg., 48-bit Q reg., 6 15-bit B registers, miscellaneous	Variable (24- or 48-bit)	Multiple types of jump and skip	Big
CDC 6000 Central Processor (CP)	60		1964	3	Register–Register	n/a [lower-alpha 2]	24 (8 18-bit address reg., 8 18-bit index reg., 8 60-bit operand reg.)	Variable (15-, 30-, or 60-bit)	Compare and branch	n/a [lower-alpha 3]	Compare/Move Unit	No	No
CDC 6000 Peripheral Processor (PP)	12		1964	1 or 2	Register–Memory	CISC	1 18-bit A register, locations 1–63 serve as index registers for some instructions	Variable (12- or 24-bit)	Test A register, test channel	n/a [lower-alpha 4]	additional Peripheral Processing Units	No	No
Crusoe (native VLIW)	32 [17]		2000	1	Register–Register	VLIW [17] [18]	1 in native push stack mode 6 in x86 emulation + 8 in x87/MMX mode + 50 in rename status 12 integer + 48 shadow + 4 debug in native VLIW mode [17] [18]	Variable (64- or 128-bit in native mode, 15 bytes in x86 emulation) [18]	Condition code [17]	Little
Elbrus 2000 (native VLIW)	64	v6	2007	1	Register–Register [17]	VLIW	8–64	64	Condition code	Little	Just-in-time dynamic translation: x87, IA-32, MMX, SSE, SSE2, x86-64, SSE3, AVX	No	No
DLX	32	?	1990	3	?	RISC	32	Fixed (32-bit)	?	Big	?	Yes	?
eSi-RISC	16/32		2009	3	Register–Register	RISC	8–72	Variable (16- or 32-bit)	Compare and branch and condition register	Bi	User-defined instructions	No	No
iAPX 432 [19]	32		1981	3	Stack machine	CISC	0	Variable (6 to 321 bits)				No	No
Itanium (IA-64)	64		2001		Register–Register	EPIC	128	Fixed (128-bit bundles with 5-bit template tag and 3 instructions, each 41-bit long)	Condition register	Bi (selectable)	Intel Virtualization Technology	No	No
LoongArch	32, 64		2021	4	Register–Register	RISC	32 (including "zero")	Fixed (32-bit)		Little		No	No
M32R	32		1997	3	Register–Register	RISC	16	Variable (16- or 32-bit)	Condition register	Bi
m88k	32		1988	3	Register–Register	RISC		Fixed (32-bit)		Big
Mico32	32	?	2006	3	Register–Register	RISC	32 [20]	Fixed (32-bit)	Compare and branch	Big	User-defined instructions	Yes [21]	Yes
MIPS	64 (32→64)	6 [22] [23]	1981	1–3	Register–Register	RISC	4–32 (including "zero")	Fixed (32-bit)	Condition register	Bi	MDMX, MIPS-3D	No	No [24] [25]
MMIX	64	?	1999	3	Register–Register	RISC	256	Fixed (32-bit)	Condition register	Big	?	Yes	Yes
Nios II	32	?	2000	3	Register–Register	RISC	32	Fixed (32-bit)	Condition register	Little	Soft processor that can be instantiated on an Altera FPGA device	No	On Altera/Intel FPGA only
NS320xx	32		1982	5	Memory–Memory	CISC	8	Variable Huffman coded, up to 23 bytes long	Condition code	Little	BitBlt instructions
OpenRISC	32, 64	1.4 [26]	2000	3	Register–Register	RISC	16 or 32	Fixed	Condition code	Bi	?	Yes	Yes
PA-RISC (HP/PA)	64 (32→64)	2.0	1986	3	Register–Register	RISC	32	Fixed (32-bit)	Compare and branch	Big → Bi	MAX	No
PDP-8 [27]	12		1966		Register–Memory	CISC	1 accumulator 1 multiplier quotient register	Fixed (12-bit)	Condition register Test and branch		EAE (Extended Arithmetic Element)
PDP-11	16		1970	2	Memory–Memory	CISC	8 (includes program counter and stack pointer, though any register can act as stack pointer)	Variable (16-, 32-, or 48-bit)	Condition code	Little	Extended Instruction Set, Floating Instruction Set, Floating Point Processor, Commercial Instruction Set	No	No
POWER, PowerPC, Power ISA	32/64 (32→64)	3.1 [28]	1990	3 (mostly). FMA, LD/ST-Update	Register–Register	RISC	32 GPR, 8 4-bit Condition Fields, Link Register, Counter Register	Fixed (32-bit), Variable (32- or 64-bit with the 32-bit prefix [28] )	Condition code, Branch-Counter auto-decrement	Bi	AltiVec, APU, VSX, Cell, Floating-point, Matrix Multiply Assist	Yes	Yes
RISC-V	32, 64, 128	20191213 [29]	2010	3	Register–Register	RISC	32 (including "zero")	Variable	Compare and branch	Little	?	Yes	Yes
RX	64/32/16		2000	3	Memory–Memory	CISC	4 integer + 4 address	Variable	Compare and branch	Little			No
S+core	16/32		2005			RISC				Little
SPARC	64 (32→64)	OSA2017 [30]	1985	3	Register–Register	RISC	32 (including "zero")	Fixed (32-bit)	Condition code	Big → Bi	VIS	Yes	Yes [31]
SuperH (SH)	32	?	1994	2	Register–Register Register–Memory	RISC	16	Fixed (16- or 32-bit), Variable	Condition code (single bit)	Bi	?	Yes	Yes
System/360 System/370 z/Architecture	64 (32→64)		1964	2 (most) 3 (FMA, distinct operand facility) 4 (some vector inst.)	Register–Memory Memory–Memory Register–Register	CISC	16 general 16 control (S/370 and later) 16 access (ESA/370 and later)	Variable (16-, 32-, or 48-bit)	Condition code, compare and branch auto increment, Branch-Counter auto-decrement	Big		No	No
TMS320 C6000 series	32		1983	3	Register-Register	VLIW	32 on C67x 64 on C67x+	Fixed (256-bit bundles with 8 instructions, each 32-bit long)	Condition register	Bi		No	No
Transputer	32 (4→64)		1987	1	Stack machine	MISC	3 (as stack)	Fixed (8-bit)	Compare and branch	Little
VAX	32		1977	6	Memory–Memory	CISC	16	Variable	Condition code, compare and branch	Little		No
Z80	8		1976	2	Register–Memory	CISC	17	Variable (8 to 32 bits)	Condition register	Little
Archi- tecture	Bits	Version	Intro- duced	Max # operands	Type	Design	Registers (excluding FP/vector)	Instruction encoding	Branch evaluation	Endian- ness	Extensions	Open	Royalty free

See also

• Central processing unit (CPU)
• Processor design
• Comparison of CPU microarchitectures
• Instruction set architecture
• Microprocessor
• Benchmark (computing)

Notes

1. The LEA (all processors) and IMUL-immediate (80186 & later) instructions accept three operands; most other instructions of the base integer ISA accept no more than two operands.
2. partly RISC: load/store architecture and simple addressing modes, partly CISC: three instruction lengths and no single instruction timing
3. Since memory is an array of 60-bit words with no means to access sub-units, big endian vs. little endian makes no sense. The optional CMU unit uses big-endian semantics.
4. Since memory is an array of 12-bit words with no means to access sub-units, big endian vs. little endian makes no sense.

References

1. da Cruz, Frank (October 18, 2004). "The IBM Naval Ordnance Research Calculator". Columbia University Computing History. Retrieved May 8, 2024.
2. "Russian Virtual Computer Museum _ Hall of Fame _ Nikolay Petrovich Brusentsov".
3. Trogemann, Georg; Nitussov, Alexander Y.; Ernst, Wolfgang (2001). Computing in Russia: the history of computer devices and information technology revealed. Vieweg+Teubner Verlag. pp. 19, 55, 57, 91, 104–107. ISBN   978-3-528-05757-2..
4. 650 magnetic drum data processing machine (PDF). IBM. June 1955. 22-6060-2. Retrieved May 8, 2024.
5. IBM 7070-7074 Principles of Operation (PDF). Systems Reference Library. IBM. 1962. GA22-7003-6. Retrieved May 8, 2024.
6. UNIVAC® Solid-state 80 Computer (PDF). Sperry Rand Corporation. 1959. U1742.1r3. Retrieved May 8, 2024.
7. IBM 650 MDDPM Additional Features - Indexing Accumulators - Floating-Decimal Arithmetic - Advanced Write-Up (PDF). IBM. 1955. 22-6258-0. Retrieved May 8, 2024.
8. "AMD64 Architecture Programmer's Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions" (PDF). AMD. November 2009.
9. "Synopsys Introduces New 64-bit ARC Processor IP Delivering up to 3x Performance Increase for High-End Embedded Applications".
10. "ARMv8 Technology Preview" (PDF). Archived from the original (PDF) on 2018-06-10. Retrieved 2011-10-28.
11. "ARM goes 64-bit with new ARMv8 chip architecture". Computerworld . 27 October 2011. Retrieved 8 May 2024.
12. Toshio Yoshida. "Hot Chips 30 conference; Fujitsu briefing" (PDF). Fujitsu. Archived from the original (PDF) on 2020-12-05.
13. "AVR32 Architecture Document" (PDF). Atmel . Retrieved 2024-05-08.
14. "Blackfin manual" (PDF). analog.com.
15. "Blackfin Processor Architecture Overview". Analog Devices . Retrieved 2024-05-08.
16. "Blackfin memory architecture". Analog Devices. Archived from the original on 2011-06-16. Retrieved 2009-12-18.
17. "Crusoe Exposed: Transmeta TM5xxx Architecture 2". Real World Technologies.
18. Alexander Klaiber (January 2000). "The Technology Behind Crusoe Processors" (PDF). Transmeta Corporation. Retrieved December 6, 2013.
19. Intel Corporation (1981). Introduction to the iAPX 432 Architecture (PDF). pp. iii.
20. "LatticeMico32 Architecture". Lattice Semiconductor. Archived from the original on 23 June 2010.
21. "LatticeMico32 Open Source Licensing". Lattice Semiconductor. Archived from the original on 20 June 2010.
22. MIPS64 Architecture for Programmers: Release 6
23. MIPS32 Architecture for Programmers: Release 6
24. MIPS Open
25. "Wave Computing Closes Its MIPS Open Initiative with Immediate Effect, Zero Warning".
26. OpenRISC Architecture Revisions
27. "PDP-8 Users Handbook" (PDF). bitsavers.org. 2019-02-16.
28. "Power ISA Version 3.1". openpowerfoundation.org. 2020-05-01. Retrieved 2021-10-20.
29. "RISC-V ISA Specifications" . Retrieved 17 June 2019.
30. Oracle SPARC Processor Documentation
31. SPARC Architecture License