Comparison of CPU microarchitectures

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The following is a comparison of CPU microarchitectures .

Contents

MicroarchitectureYearPipeline stagesMisc
Elbrus-8S 2014 VLIW, Elbrus (proprietary, closed) version 5, 64-bit
AMD K5 19965 Superscalar, branch prediction, speculative execution, out-of-order execution, register renaming [lower-alpha 1]
AMD K6 19976 Superscalar, branch prediction, speculative execution, out-of-order execution, register renaming [lower-alpha 2]
AMD K6-III 1999 Branch prediction, speculative execution, out-of-order execution [1]
AMD K7 1999Out-of-order execution, branch prediction, Harvard architecture
AMD K8 200364-bit, integrated memory controller, 16 byte instruction prefetching
AMD K10 2007Superscalar, out-of-order execution, 32-way set associative L3 victim cache, 32-byte instruction prefetching
ARM7TDMI (-S) 20013
ARM7EJ-S 20015
ARM8105static branch prediction, double-bandwidth memory
ARM9TDMI19985
ARM1020E6
XScale PXA210/PXA250 20027
ARM1136J(F)-S 8
ARM1156T2(F)-S 9
ARM Cortex-A5 8Multi-core, single issue, in-order
ARM Cortex-A7 MPCore 8Partial dual-issue, in-order, 2-way set associative level 1 instruction cache
ARM Cortex-A8 200513Dual-issue, in-order, speculative execution, superscalar, 2-way pipeline decode
ARM Cortex-A9 MPCore 20078–11Out-of-order, speculative issue, superscalar
ARM Cortex-A15 MPCore 201015Multi-core (up to 16), out-of-order, speculative issue, 3-way superscalar
ARM Cortex-A53 2012Partial dual-issue, in-order
ARM Cortex-A55 20178in-order, speculative execution
ARM Cortex-A57 2012Deeply out-of-order, wide multi-issue, 3-way superscalar
ARM Cortex-A72 2015
ARM Cortex-A73 2016Out-of-order superscalar
ARM Cortex-A75 201711–13Out-of-order superscalar, speculative execution, register renaming, 3-way
ARM Cortex-A76 201813Out-of-order superscalar, 4-way pipeline decode
ARM Cortex-A77 201913Out-of-order superscalar, speculative execution, register renaming, 6-way pipeline decode, 10-issue, branch prediction, L3 cache
ARM Cortex-A78 202013Out-of-order superscalar, register renaming, 4-way pipeline decode, 6 instruction per cycle, branch prediction, L3 cache
ARM Cortex-A710 202110
ARM Cortex-X1 2020135-wide decode out-of-order superscalar, L3 cache
ARM Cortex-X2 202110
ARM Cortex-X3 20229
ARM Cortex-X4 202310
AVR32 AP7 7
AVR32 UC3 3Harvard architecture
Bobcat 2011Out-of-order execution
Bulldozer 201120Shared multithreaded L2 cache, multithreading, multi-core, around 20 stage long pipeline, integrated memory controller, out-of-order, superscalar, up to 16 cores per chip, up to 16 MB L3 cache, Virtualization, Turbo Core, FlexFPU which uses simultaneous multithreading [2]
Piledriver 2012Shared multithreaded L2 cache, multithreading, multi-core, around 20 stage long pipeline, integrated memory controller, out-of-order, superscalar, up to 16 MB L2 cache, up to 16 MB L3 cache, Virtualization, FlexFPU which use simultaneous multithreading, [2] up to 16 cores per chip, up to 5 GHz clock speed, up to 220 W TDP, Turbo Core
Steamroller 2014Multi-core, branch prediction
Excavator 201520Multi-core
Zen 201719Multi-core, superscalar, 2-way simultaneous multithreading, 4-way decode, out-of-order execution, L3 cache
Zen+ 201819Multi-core, superscalar, 4-way decode, out-of-order execution, L3 cache
Zen 2 201919Multi-chip module, multi-core, superscalar, 4-way decode, out-of-order execution, L3 cache
Zen 3 202019Multi-chip module, multi-core, superscalar, 4-way decode, out-of-order execution, SMT, L3 cache
Zen 4 2022Multi-chip module, multi-core, superscalar, L3 cache
Crusoe 2000In-order execution, 128-bit VLIW, integrated memory controller
Efficeon 2004In-order execution, 256-bit VLIW, fully integrated memory controller
Cyrix Cx5x86 19956 [3] Branch prediction
Cyrix 6x86 1996Superscalar, superpipelined, register renaming, speculative execution, out-of-order execution
DLX 5
eSi-3200 5In-order, speculative issue
eSi-3250 5In-order, speculative issue
EV4 (Alpha 21064) Superscalar
EV7 (Alpha 21364) Superscalar design with out-of-order execution, branch prediction, 4-way simultaneous multithreading, integrated memory controller
EV8 (Alpha 21464) Superscalar design with out-of-order execution
65k Ultra low power consumption, register renaming, out-of-order execution, branch prediction, multi-core, module, capable of reach higher clock
P5 (Pentium)19935Superscalar
P6 (Pentium Pro)14Speculative execution, register renaming, superscalar design with out-of-order execution
P6 (Pentium II)14 [4] Branch prediction
P6 (Pentium III)199514 [4]
Intel Itanium "Merced"2001Single core, L3 cache
Intel Itanium 2 "McKinley"200211 [5] Speculative execution, branch prediction, register renaming, 30 execution units, multithreading, multi-core, coarse-grained multithreading, 2-way simultaneous multithreading, Dual-domain multithreading, Turbo Boost, Virtualization, VLIW, RAS with Advanced Machine Check Architecture, Instruction Replay technology, Cache Safe technology, Enhanced SpeedStep technology
Intel NetBurst (Willamette)2000202-way simultaneous multithreading (Hyper-threading), Rapid Execution Engine, Execution Trace Cache, quad-pumped Front-Side Bus, Hyper-pipelined Technology, superscalar, out-of order
NetBurst (Northwood)2002202-way simultaneous multithreading
NetBurst (Prescott)2004312-way simultaneous multithreading
NetBurst (Cedar Mill)2006312-way simultaneous multithreading
Intel Core 200612Multi-core, out-of-order, 4-way superscalar
Intel Atom 162-way simultaneous multithreading, in-order, no instruction reordering, speculative execution, or register renaming
Intel Atom Oak Trail2-way simultaneous multithreading, in-order, burst mode, 512 KB L2 cache
Intel Atom Bonnell 2008SMT
Intel Atom Silvermont 2013Out-of-order execution
Intel Atom Goldmont 2016Multi-core, out-of-order execution, 3-wide superscalar pipeline, L2 cache
Intel Atom Goldmont Plus 2017Multi-core
Intel Atom Tremont 2019Multi-core, superscalar, out-of-order execution, speculative execution, register renaming
Intel Atom Gracemont2021Multi-core, superscalar, out-of-order execution, speculative execution, register renaming
Intel Atom Crestmont2023Multi-core
Intel Atom Skymont2024Multi-core
Nehalem 2008142-way simultaneous multithreading, out-of-order, 6-way superscalar, integrated memory controller, L1/L2/L3 cache, Turbo Boost
Sandy Bridge 2011142-way simultaneous multithreading, multi-core, on-die graphics and PCIe controller, system agent with integrated memory and display controller, ring interconnect, L1/L2/L3 cache, micro-op cache, 2 threads per core, Turbo Boost,
Intel Haswell 201314–19 SoC design, multi-core, multithreading, 2-way simultaneous multithreading, hardware-based transactional memory (in selected models), L4 cache (in GT3 models), Turbo Boost, out-of-order execution, superscalar, up to 8 MB L3 cache (mainstream), up to 20 MB L3 cache (Extreme)
Broadwell 201414–19Multi-core, multithreading
Skylake 201514–19Multi-core, L4 cache on certain Skylake-R, Skylake-U and Skylake-Y models. On-package PCH on U, Y, m3, m5 and m7 models. 5 wide superscalar/5 issues.
Kaby Lake 201614–19Multi-core, L4 cache on certain low and ultra low power models (Kaby Lake-U and Kaby Lake-Y),
Intel Sunny Cove201914–20Multicore, 2-way multithreading, massive OoOE engine, 5 wide superscalar/5 issue.
Intel Cypress Cove202114multicore, 5 wide superscalar/6 issues, massive OoOE engine, big core design.
Intel Willow Cove2020Multicore, SMT
Intel Golden Cove2021Multicore, SMT
Intel Redwood Cove2023Multicore, SMT
Intel Lion Cove2024Multicore, without SMT
Intel Xeon Phi 7120x20137-stage integer, 6-stage vectorMulti-core, multithreading, 4 hardware-based simultaneous threads per core which can't be disabled unlike regular HyperThreading, Time-multiplexed multithreading, 61 cores per chip, 244 threads per chip, 30.5 MB L2 cache, 300 W TDP, Turbo Boost, in-order dual-issue pipelines, coprocessor, Floating-point accelerator, 512-bit wide Vector-FPU
LatticeMico32 20066Harvard architecture
Nvidia Denver2014Multicore, superscalar, 2-way decode, L2
Nvidia Carmel2018Multicore, 10-way superscalar, L3
POWER1 1990Superscalar, out-of-order execution
POWER3 1998Superscalar, out-of-order execution
POWER4 2001Superscalar, speculative execution, out-of-order execution
POWER5 20042-way simultaneous multithreading, out-of-order execution, integrated memory controller
IBM POWER6 20072-way simultaneous multithreading, in-order execution, up to 5 GHz
IBM POWER7+Multi-core, multithreading, out-of-order, superscalar, 4 intelligent simultaneous threads per core, 12 execution units per core, 8 cores per chip, 80 MB L3 cache, true hardware entropy generator, hardware-assisted cryptographic acceleration, fixed-point unit, decimal fixed-point unit, Turbo Core, decimal floating-point unit
IBM POWER8 201315–23Superscalar, L4 cache
IBM POWER9 201712–16Superscalar, out-of-order execution, L4 cache
IBM Power10 2021Superscalar
IBM Cell 2006Multi-core, multithreading, 2-way simultaneous multithreading (PPE), Power Processor Element, Synergistic Processing Elements, Element Interconnect Bus, in-order execution
IBM Cyclops64 Multi-core, multithreading, 2 threads per core, in-order
IBM zEnterprise zEC12 201215/16/17Multi-core, 6 cores per chip, up to 5.5  GHz, superscalar, out-of-order, 48  MB L3 cache, 384 MB shared L4 cache
IBM A2 15multicore, 4-way simultaneous multithreaded
PowerPC 401 19963
PowerPC 405 19985
PowerPC 440 19997
PowerPC 470 20099 Symmetric multiprocessing (SMP)
PowerPC e300 4Superscalar, branch prediction
PowerPC e500 Dual 7 stageMulti-core
PowerPC e600 3-issue 7 stageSuperscalar out-of-order execution, branch prediction
PowerPC e5500 20104-issue 7 stageOut-of-order, multi-core
PowerPC e6500 2012Multi-core
PowerPC 603 45 execution units, branch prediction, no SMP
PowerPC 603q 19965In-order
PowerPC 604 19946Superscalar, out-of-order execution, 6 execution units, SMP support
PowerPC 620 19975Out-of-order execution, SMP support
PWRficient PA6T2007Superscalar, out-of-order execution, 6 execution units
R4000 19918Scalar
StrongARM SA-110 19965Scalar, in-order
SuperH SH2 5
SuperH SH2A 20065Superscalar, Harvard architecture
SPARC Superscalar
hyperSPARC 1993Superscalar
SuperSPARC 1992Superscalar, in-order
SPARC64 VI/VII/VII+2007Superscalar, out-of-order [6]
UltraSPARC 19959
UltraSPARC T1 20056Open source, multithreading, multi-core, 4 threads per core, scalar, in-order, integrated memory controller, 1 FPU
UltraSPARC T2 20078Open source, multithreading, multi-core, 8 threads per core
SPARC T3 20108Multithreading, multi-core, 8 threads per core, SMP, 16 cores per chip, 2 MB L3 cache, in-order, hardware random number generator
Oracle SPARC T4 201116Multithreading, multi-core, 8 fine-grained threads per core of which 2 can be executed simultaneously, 2-way simultaneous multithreading, SMP, 8 cores per chip, out-of-order, 4 MB L3 cache, out-of order, Hardware random number generator
Oracle Corporation SPARC T5 201316Multithreading, multi-core, 8 fine-grained threads per core of which 2 can be executed simultaneously, 2-way simultaneous multithreading, 16 cores per chip, out-of-order, 16-way associative shared 8 MB L3 cache, hardware-assisted cryptographic acceleration, stream-processing unit, out-of order execution, RAS features, 16 cryptography units per chip, hardware random number generator
Oracle SPARC M516Multithreading, multi-core, 8 fine-grained threads per core of which 2 can be executed simultaneously, 2-way simultaneous multithreading, 6 cores per chip, out-of-order, 48 MB L3 cache, out-of order execution, RAS features, stream-processing unit, hardware-assisted cryptographic acceleration, 6 cryptography units per chip, Hardware random number generator
Fujitsu SPARC64 XMultithreading, multi-core, 2-way simultaneous multithreading, 16 cores per chip, out-of order, 24 MB L2 cache, out-of order, RAS features
Imagination Technologies MIPS Warrior
VIA C7 2005In-order execution
VIA Nano (Isaiah)2008Superscalar out-of-order execution, branch prediction, 7 execution units
WinChip 19974In-order execution

See also

Notes

  1. According to AMDs K5 data sheet. The design incorporates many ideas and functional parts from AMDs Am29000 32-bit RISC microprocessor design.
  2. According to AMDs K6 data sheet. The design is based on NexGen's Nx686 and therefore not a direct successor to the K5.

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<span class="mw-page-title-main">AMD K6</span> Computer microprocessor

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<span class="mw-page-title-main">Pentium (original)</span> Intel microprocessor

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x86 Family of instruction set architectures

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<span class="mw-page-title-main">Graphics card</span> Expansion card which generates a feed of output images to a display device

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x86-64 64-bit version of x86 architecture

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<span class="mw-page-title-main">Graphics processing unit</span> Specialized electronic circuit; graphics accelerator

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A processor register is a quickly accessible location available to a computer's processor. Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. In computer architecture, registers are typically addressed by mechanisms other than main memory, but may in some cases be assigned a memory address e.g. DEC PDP-10, ICT 1900.

<span class="mw-page-title-main">AMD K5</span> Microarchitecture

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<span class="mw-page-title-main">AMD Am29000</span> Family of RISC microprocessors and microcontrollers

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x87 is a floating-point-related subset of the x86 architecture instruction set. It originated as an extension of the 8086 instruction set in the form of optional floating-point coprocessors that work in tandem with corresponding x86 CPUs. These microchips have names ending in "87". This is also known as the NPX. Like other extensions to the basic instruction set, x87 instructions are not strictly needed to construct working programs, but provide hardware and microcode implementations of common numerical tasks, allowing these tasks to be performed much faster than corresponding machine code routines can. The x87 instruction set includes instructions for basic floating-point operations such as addition, subtraction and comparison, but also for more complex numerical operations, such as the computation of the tangent function and its inverse, for example.

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<span class="mw-page-title-main">Dell Precision</span> Series of computer workstations

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<span class="mw-page-title-main">Intel Management Engine</span> Autonomous computer subsystem

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<span class="mw-page-title-main">Hardware-based encryption</span> Use of computer hardware to assist software in the process of data encryption

Hardware-based encryption is the use of computer hardware to assist software, or sometimes replace software, in the process of data encryption. Typically, this is implemented as part of the processor's instruction set. For example, the AES encryption algorithm can be implemented using the AES instruction set on the ubiquitous x86 architecture. Such instructions also exist on the ARM architecture. However, more unusual systems exist where the cryptography module is separate from the central processor, instead being implemented as a coprocessor, in particular a secure cryptoprocessor or cryptographic accelerator, of which an example is the IBM 4758, or its successor, the IBM 4764. Hardware implementations can be faster and less prone to exploitation than traditional software implementations, and furthermore can be protected against tampering.

References

  1. "Products We Design". amd.com. Retrieved 19 January 2014.
  2. 1 2 "wp-content/uploads/2013/07/AMD-Steamroller-vs-Bulldozer". cdn3.wccftech.com. Archived from the original on 17 October 2013. Retrieved 19 January 2014.
  3. "Cyrix 5x86 ("M1sc")". pcguide.com. Retrieved 19 January 2014.
  4. 1 2 "Computer Science 246: Computer Architecture" (PDF). Harvard University. Archived from the original (PDF) on 24 December 2013. Retrieved 23 December 2013. P6 pipeline
  5. Intel Itanium 2 Processor Hardware Developer's Manual. p. 14. http://www.intel.com/design/itanium2/manuals/25110901.pdf (2002) Retrieved 28 November 2011
  6. "Multi Core Processor SPARC64 Series : Fujitsu Global". fujitsu.com. Retrieved 19 January 2014.