Blackwell (microarchitecture)

Last updated

Blackwell
LaunchedQ4 2024
Designed by Nvidia
Manufactured by
Fabrication processTSMC 4N
Codename(s)GB100
GB20x
Product Series
Desktop
Specifications
Memory support GDDR7 (Consumer)
HBM3e (Datacenter)
PCIe support PCIe 5.0 (Consumer)
PCIe 6.0 (Datacenter)
Supported Graphics APIs
DirectX DirectX 12 Ultimate (Feature Level 12_2)
Direct3D Direct3D 12
Shader Model Shader Model 6.8
OpenCL OpenCL 3.0
OpenGL OpenGL 4.6
Vulkan Vulkan 1.4
Supported Compute APIs
CUDA Compute Capability 10.x
Compute Capability 12.x
DirectCompute Yes
Media Engine
Encoder(s) supported NVENC
History
Predecessor Ada Lovelace (consumer)
Hopper (datacenter)
Successor Rubin

Blackwell is a graphics processing unit (GPU) microarchitecture developed by Nvidia as the successor to the Hopper and Ada Lovelace microarchitectures.

Contents

Named after statistician and mathematician David Blackwell, the name of the Blackwell architecture was leaked in 2022 with the B40 and B100 accelerators being confirmed in October 2023 with an official Nvidia roadmap shown during an investors presentation. [1] It was officially announced at Nvidia's GTC 2024 keynote on March 18, 2024. [2]

After the lackluster performance together with high pricing for AIB partner cards, the 5000-series architecture was also called “Blacksheep” by some fans.

History

David Blackwell (1919-2010) David Blackwell 1999 (re-scanned, cropped).jpg
David Blackwell (1919–2010)

In March 2022, Nvidia announced the Hopper datacenter architecture for AI accelerators. Demand for Hopper products was high throughout 2023's AI hype. [3] The lead time from order to delivery of H100-based servers was between 36 and 52 weeks due to shortages and high demand. [4] Nvidia reportedly sold 500,000 Hopper-based H100 accelerators in Q3 2023 alone. [4] Nvidia's AI dominance with Hopper products led to the company increasing its market capitalization to over $2 trillion, behind only Microsoft and Apple. [5]

The Blackwell architecture is named after American mathematician David Blackwell who was known for his contributions to the mathematical fields of game theory, probability theory, information theory, and statistics. These areas have influenced or are implemented in transformer-based generative AI model designs or their training algorithms. Blackwell was the first African American scholar to be inducted into the National Academy of Sciences. [6]

In Nvidia's October 2023 Investor Presentation, its datacenter roadmap was updated to include reference to its B100 and B40 accelerators and the Blackwell architecture. [7] [8] Previously, the successor to Hopper was simply named on roadmaps as "Hopper-Next". Nvidia's updated roadmap emphasized the move from a two-year release cadence for datacenter products to yearly releases targeted for x86 and ARM systems.

At the Graphics Technology Conference (GTC) on March 18, 2024, Nvidia officially announced the Blackwell architecture with focus placed on its B100 and B200 datacenter accelerators and associated products, such as the eight-GPU HGX B200 board and the 72-GPU NVL72 rack-scale system. [9] Nvidia CEO Jensen Huang said that with Blackwell, "we created a processor for the generative AI era" and emphasized the overall Blackwell platform combining Blackwell accelerators with Nvidia's ARM-based Grace CPU. [10] [11] Nvidia touted endorsements of Blackwell from the CEOs of Google, Meta, Microsoft, OpenAI and Oracle. [11] The keynote did not mention gaming.

It was reported in October 2024 that there was a design flaw in the Blackwell architecture that had been fixed in collaboration with TSMC. [12] According to Huang, the design flaw was "functional" and "caused the yield[s] to be low". [13] By November 2024, Morgan Stanley was reporting that "the entire 2025 production" of Blackwell silicon was "already sold out". [14]

During the company's CES 2025 keynote, Nvidia announced that the foundation models for Blackwell will include models from Black Forest Labs (Flux), Meta AI, Mistral AI, and Stability AI. [15]

Architecture

Blackwell is an architecture designed for both datacenter compute applications and for gaming and workstation applications with dedicated dies for each purpose.

Process node

Blackwell is fabricated on the custom 4NP node from TSMC. 4NP is an enhancement of the 4N node used for the Hopper and Ada Lovelace architectures. The Nvidia-specific 4NP process likely adds metal layers to the standard TSMC N4P technology. [16] The GB100 die contains 104 billion transistors, a 30% increase over the 80 billion transistors in the previous generation Hopper GH100 die. [17] As Blackwell cannot reap the benefits that come with a major process node advancement, it must achieve power efficiency and performance gains through underlying architectural changes. [18]

The GB100 die is at the reticle limit of semiconductor fabrication. [19] The reticle limit in semiconductor fabrication is the maximum size of features that lithography machines can etch into a silicon die. Previously, Nvidia had nearly hit TSMC's reticle limit with GH100's 814 mm2 die. In order to not be constrained by die size, Nvidia's B100 accelerator utilizes two GB100 dies in a single package, connected with a 10 TB/s link that Nvidia calls the NV-High Bandwidth Interface (NV-HBI). NV-HBI is based on the NVLink 5.0 protocol. Nvidia CEO Jensen Huang claimed in an interview with CNBC that Nvidia had spent around $10 billion in research and development for Blackwell's NV-HBI die interconnect. Veteran semiconductor engineer Jim Keller, who had worked on AMD's K7, K12 and Zen architectures, criticized this figure and claimed that the same outcome could be achieved for $1 billion through using Ultra Ethernet rather than the proprietary NVLink system. [20] The two connected GB100 dies are able to act like a large monolithic piece of silicon with full cache coherency between both dies. [21] The dual die package totals 208 billion transistors. [19] Those two GB100 dies are placed on top of a silicon interposer produced using TSMC's CoWoS-L 2.5D packaging technique. [22]

On the consumer side, Blackwell's largest die, GB202, measures in at 750mm2 which is 20% larger than AD102, Ada Lovelace's largest die. [23] GB202 contains a total of 24,576 CUDA cores, 28.5% more than the 18,432 CUDA cores in AD102. GB202 is the largest consumer die designed by Nvidia since the 754mm2 TU102 die in 2018, based on the Turing microarchitecture. The gap between GB202 and GB203 has also gotten much wider compared to previous generations. GB202 features more than double the number of CUDA cores than GB203 which was not the case with AD102 over AD103.

Streaming multiprocessor

CUDA cores

CUDA Compute Capability 10.0 and Compute Capability 12.0 are added with Blackwell. [24]

Tensor cores

The Blackwell architecture introduces fifth-generation Tensor Cores for AI compute and performing floating-point calculations. In the data center, Blackwell adds support for FP4 and FP6 data types. [25] The previous Hopper architecture introduced the Transformer Engine, software to facilitate quantization of higher-precision models (e.g., FP32) to lower precision, for which Hopper has greater throughput. Blackwell's second generation Transformer Engine adds support for the newer, less-precise FP4 and FP6 types. Using 4-bit data allows greater efficiency and throughput for model inference during generative AI training. [18] Nvidia claims 20 petaflops (excluding the 2x gain the company claims for sparsity) of FP4 compute for the dual-GPU GB200 superchip. [26]

Blackwell dies

Datacenter

Die GB100
Variant(s)
Release dateDec 2024
Cores CUDA Cores
TMUs
ROPs
RT Cores
Tensor Cores
Streaming Multiprocessors
CacheL1
L2
Memory interface8192-bit
Die size
Transistor count104 bn.
Transistor density
Package socketSXM6
ProductsB100
B200

Consumer

Die GB202 GB203 GB205 GB206 GB207
Variant(s)GB202-400-A1GB203-200-A1
GB203-400-A1
GB205-300-A1
Release dateJan 30, 2025Jan 30, 2025Feb 2025Mar 2025TBA
Cores CUDA Cores 24,57610,7526,4004,6082,560
TMUs 76833620014480
ROPs 192112804832
RT Cores 19284503620
Tensor Cores 76833620014480
SMs19284503620
GPCs127532
CacheL124 MB10.5 MB6.25 MB4.5 MB2.5 MB
L2128 MB64 MB48 MB32 MB32 MB
Memory interface512-bit256-bit192-bit128-bit128-bit
Die size750 mm2378 mm2263 mm2
Transistor count92.2 bn.45.6 bn.31.1 bn.
Transistor density122.6 MTr/mm2120.6 MTr/mm2118.3 MTr/mm2
Products
ConsumerDesktopRTX 5090
RTX 5090 D
RTX 5070 Ti
RTX 5080   
RTX 5070
MobileRTX 5080 Laptop
RTX 5090 Laptop
RTX 5070 Ti LaptopRTX 5070 Laptop
WorkstationDesktop
Mobile

See also

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