CDNA (microarchitecture)

Last updated

AMD CDNA
AMD CDNA wordmark.png
Release dateNovember 16, 2020
(3 years ago) (2020-11-16)
Designed by AMD
Fabrication process
History
Predecessor AMD FirePro
Variant RDNA (consumer, professional)

CDNA (Compute DNA) is a compute centered Graphics Processing Unit (GPU) microarchitecture made by Advanced Micro Devices (AMD) for datacenters. CDNA is a successor to the Graphics Core Next (GCN) microarchitecture, the other successor is RDNA (Radeon DNA), a consumer graphics focused microarchitecture. CDNA was first announced on March 5th, 2020, [2] and was featured in the AMD Instinct MI100, launched November 16th, 2020. [3] This is CDNA's only produced product, manufactured on TSMC's N7 FinFET process.

Contents

The second Iteration of the CDNA line implements a Multi Chip Module (MCM) approach, differing from its predecessor's monolithic approach. Featured in the AMD Instinct MI250x, MI250, this MCM design used an Elevated Fanout Bridge (EFB) [4] to connect the dies. These two products were announced November 8th, 2021, and launched November 11th. The CDNA 2 line contains an additional latecomer using a monolithic design, the MI210. [5] The MI250x and MI250 are the first AMD product to use the Open Compute Project (OCP)'s OCP Accelerator Module (OAM) socket form factor. Lower wattage PCIE versions are available.

The third iteration of CDNA switches to a MCM design utilizing different chiplets manufactured on multiple nodes. Currently consisting of the MI300, this products contains 15 unique dies and is connected with advanced 3D packaging techniques. The MI300 was announced January 5th 2023, and is claimed to launch H2, 2023. [6]

CDNA 1

AMD CDNA 1
Release dateNovember 16, 2020
(3 years ago) (2020-11-16)
Fabrication processTSMC N7 (FinFET)
History
Predecessor AMD FirePro
Successor CDNA 2

The CDNA family consists of one die, named Arcturus. The die is 750 millimeters squared, contains 25.6 billion transistors and is manufactured on TSMC's N7 node. [7] The Arcturus die posses 120 Compute Units, and a 4096 bit memory bus, connected to four HBM2 placements, giving the die 32 GB of memory, and just over 1200 GB/s of memory bandwidth. Compared to its predecessor, CDNA has removed all hardware related to graphics acceleration. This removal includes but is not limited to: graphics caches, tessellation hardware, Render Output units (ROPs), and the display engine. CDNA retains VCN for HEVC, H.264, and VP9 decoding. [8] CDNA has also added dedicated matrix compute hardware, similar to those added in Nvidia's Volta Architecure.

Architecture

The 120 Compute Units (CU) are organized into 4 Asynchronous Compute Engines (ACE), each ACE maintains its own independent command execution and dispatch. At the CU level, CDNA Units are organized similarly to GCN units. Every CU contains four SIMD16, that each execute their 64 thread wavefront (Wave64) over four cycles.

Memory System

CDNA has had a 20% clock bump for the HBM, resulting in roughly 200 GB/S bandwidth increase vs Vega 20 (GCN 5.0). The die has a shared 4 MB L2 cache that puts out 2kB per clock to the CU's. At the CU level each CU has its own L1 cache, a Local Data Store (LDS) with 64 kB per CU and a 4 kB Global Data Store (GDS), shared by all CUs. This GDS can be used to store control data, reduction operations or act as a small global shared surface. [8] [9]

Experimental PIM Implementation

In October 2022, Samsung demonstrated a Processing-In-Memory (PIM) specialized version of the MI100. In December 2022 Samsung showed off a cluster of 96 modified MI100s, boasting large increases in processing throughput for various workloads and significant reduction in power consumption. [10]

Changes from GCN

The Individual compute units remain incredibly similar to GCN but with the addition of 4 matrix units per CU. Support for more datatypes were added, with BF16, INT8 and INT4 being added. [8] For an extensive list of operations utilizing the matrix units and new datatypes, please reference the CDNA ISA Reference Guide.

Products

Model
(Code name)		Released Architecture
&  fab 		Transistors
& die size		Core Fillrate [lower-alpha 1] Processing power (TFLOPS) Memory TBPSoftware
interface		Physical
interface
Vector [lower-alpha 1] [lower-alpha 2] Matrix [lower-alpha 1] [lower-alpha 2]
Config [lower-alpha 3] Clock [lower-alpha 1]
(MHz)		Texture [lower-alpha 4]
(GT/s)		Pixel [lower-alpha 5]
(GP/s)		 Half
(FP16) 		Single
(FP32) 		Double
(FP64) 		INT8BF16FP16FP32FP64Bus type
& width		Size
(GB)		Clock
(MT/s)		Bandwidth
(GB/s)
AMD Instinct MI100
(Arcturus) [11] [12] 		Nov 16, 2020CDNA
TSMC   N7 		25.6×109
750 mm2		7680:480:-
120 CU		1000
1502		480
720.96		-15.72
23.10		7.86
11.5		122.88
184.57		61.44
92.28		122.88
184.57		30.72
46.14		15.36
23.07		 HBM2
4096-bit		3224001228300 W PCIe 4.0
×16		PCIe
×16
  1. 1 2 3 4 Boost values (if available) are stated below the base value in italic.
  2. 1 2 Precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  3. ↑ Unified shaders  : Texture mapping units  : Render output units and Compute units (CU)
  4. ↑ Texture fillrate is calculated as the number of texture mapping units multiplied by the base (or boost) core clock speed.
  5. ↑ Pixel fillrate is calculated as the number of render output units multiplied by the base (or boost) core clock speed.

CDNA 2

AMD CDNA 2
Release dateNovember 8, 2021
(2 years ago) (2021-11-08)
Fabrication processTSMC N6
History
Predecessor CDNA 1
Successor CDNA 3

Like CDNA, CDNA 2 also consists of one die, named Aldebaran. This die is estimated to be 790 millimeters squared, and contains 28 billion transistors while being manufactured on TSMC's N6 node. [13] The Aldebaran die contains only 112 Compute units, a 6.67% decrease from Arcturus. Like the previous generation this die contains a 4096 bit memory bus, now using HBM2e with a doubling in capacity, up to 64 GB. The largest change in CDNA 2 is the ability for two dies to be placed on the same package. The MI250x consists of 2 Aldebaran dies, 220 CU (110 per die) and 128 GB of HBM2e. These dies are connected with 4 Infinity fabric links, and addressed as independent GPUs by the host system. [14]

Architecture

The 112 CU are organized similarly to CDNA, into 4 Asynchronous Compute Engines, each with 28 CUs, instead of the prior generations 30. Like CDNA, each CU contains four SIMD16 units executing a 64 thread wavefront across 4 cycle. The 4 Matrix Engines and vector units have added support for full rate FP64, enabling significant uplift over the prior generation. [15] CDNA2 also revises multiple internal caches, doubling bandwidth across the board.

Memory System

The memory system in CDNA 2 sports across the board improvements. Starting with the move to HBM2e, doubling the quantity to 64 GB, and increasing bandwidth by roughly one third (~1200GB/s to 1600GB/s). [14] At the cache level. each GCD has a 16 way, 8 MB L2 cache that is partitioned into 32 slices. This cache puts out 4kB per clock, 128B per clock per slice, which is a doubling of the bandwidth from CDNA. [14] Additionally, the 4kB Global Data Store was removed. [15] All caches, including the L2 and LDS have support added for FP64 data.

Interconnect

CDNA2 brings forth the first product with multiple GPUs on the same package. The two gpus are connected by 4 infinity fabric links, with a total bidirectional bandwidth of 400 GB/s. [15] Each die contains 8 Infinity fabric links, each physically implemented with a 16 lane infinity link. When paired with an AMD processor, this will act as infinity fabric. if paired with any other x86 processor, this will fallback to 16 lanes of PCIE 4.0. [15]

Changes from CDNA

The largest up front change is the additional of full rate FP64 support across all compute elements. This results in a 4x increase FP64 matrix calculations, with large increases in FP64 vector calculations. [14] Additionally support for packed FP32 operations were added, with opcodes like 'V_PK_FMA_F32' and 'V_PK_MUL_F32'. [16] Packed FP32 operations can enable up to 2x throughput, but do require code modification. [14] As with CDNA, for further information on CDNA 2 operations, please reference the CDNA 2 ISA Reference Guide.

Products

CDNA 3

AMD CDNA 3
Release dateDecember 6, 2023
(4 months ago) (2023-12-06)
Fabrication processTSMC N5 & N6
History
Predecessor CDNA 2

Unlike its predecessors, CDNA 3 consists of multiple dies, used in a multi chip system, similar to AMD's Zen 2, 3 and 4 line of products. The MI300 Package is comparatively massive, with 9 chiplets produced on 5nm, placed on top of 4 6nm chiplets. [6] This is all combined with 128GB of HBM3, using 8 HBM placements. [17] This Package contains an estimated 146 Billion Transistors. This product is expected to launch the second half of 2023, and more information will become available then. [6] [17]

Products

Product Comparisons

Model
(Code name)		Release date Architecture
&  fab 		Transistors
& die size		Core Fillrate [lower-alpha 1] Vector Processing power [lower-alpha 1] [lower-alpha 2]
(TFLOPS)		Matrix Processing power [lower-alpha 1] [lower-alpha 2]
(TFLOPS)		 Memory TBPSoftware
Interface		Physical
Interface
Config [lower-alpha 3] Clock [lower-alpha 1]
(MHz)		Texture [lower-alpha 4]
(GT/s)		Pixel [lower-alpha 5]
(GP/s)		 Half (FP16) Single (FP32) Double (FP64) INT8BF16FP16FP32FP64Bus type
& width		Size
(GB)		Clock
(MT/s)		Bandwidth
(GB/s)
Tesla V100 (PCIE)
(GV100) [18] [19] 		May 10, 2017Volta
TSMC  12 nm 		12.1×109
815 mm2		5120:320:128:640
80 SM		1370438.4175.3628.0614.037.01N/AN/AN/A112.23N/AHBM2
4096 bit		16
32		1750900250 WPCIe 3.0
×16		PCIe ×16
Tesla V100 (SXM)
(GV100) [20] [21] 		May 10, 20171455465.6186.2429.8014.907.46N/AN/AN/A119.19N/A300 WNVLINKSXM2
Radeon Instinct MI50
(Vega 20) [22] [23] [24] [25] [26] [27] 		Nov 18, 2018GCN 5
TSMC  7 nm 		13.2×109
331 mm2		3840:240:64
60 CU		1450
1725		348.0
414.0		92.80
110.4		22.27
26.50		11.14
13.25		5.568
6.624		N/AN/A26.513.3 ?HBM2
4096-bit		16
32		20001024300 W PCIe 4.0
×16		PCIe
×16
Radeon Instinct MI60
(Vega 20) [23] [28] [29] [30] 		4096:256:64
64 CU		1500
1800		384.0
460.8		96.00
115.2		24.58
29.49		12.29
14.75		6.144
7.373		N/AN/A3216 ?
Tesla A100 (PCIE)
(GA100) [31] [32] 		May 14, 2020Ampere
TSMC  7 nm 		54.2×109
826 mm2		6912:432:-:432
108 SM		1065
1410		460.08
609.12		-58.89
77.97		14.72
19.49		7.36
9.75		942.24
1247.47		235.56
311.87		235.56
311.87		117.78
155.93		14.72
19.49		HBM2
5120 bit		40
80		31862039250 WPCIe 4.0
×16		PCIe ×16
Tesla A100 (SXM)
(GA100)) [33] [34] 		1275
1410		550.80
609.12		-70.50
77.97		17.63
19.49		8.81
9.75		1128.04
1247.47		282.01
311.87		282.01
311.87		141.00
155.93		17.63
19.49		400 WNVLINKSXM4
AMD Instinct MI100
(Arcturus) [35] [36] 		Nov 16, 2020CDNA
TSMC  7 nm 		25.6×109
750 mm2		7860:480:-:480
120 CU		1000
1502		480
720.96		- ?15.72
23.10		7.86
11.5		122.88
184.57		61.44
92.28		122.88
184.57		30.72
46.14		15.36
23.07		HBM2
4096-bit		3224001228300 W PCIe 4.0
×16		PCIe
×16
AMD Instinct MI250X (PCIE)
(Aldebaran)		Nov 8, 2021CDNA 2
TSMC  6 nm 		58×109
1540 mm2		14080:880:-:880
220 CU
AMD Instinct MI250X (OAM)
(Aldebaran)
Tesla H100 (PCIE)
(GH100)		Mar 22, 2022Hopper
TSMC  4 nm 		80×109
814 mm2
Tesla H100 (SXM)
(GH100)
  1. 1 2 3 4 Boost values (if available) are stated below the base value in italic.
  2. 1 2 Precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  3. ↑ Unified shaders  : Texture mapping units  : Render output units  : AI accelerators and Compute units (CU) / Streaming multiprocessors (SM)
  4. ↑ Texture fillrate is calculated as the number of texture mapping units multiplied by the base (or boost) core clock speed.
  5. ↑ Pixel fillrate is calculated as the number of render output units multiplied by the base (or boost) core clock speed.

See also

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References

  1. ↑ Smith, Ryan (June 9, 2022). "AMD: Combining CDNA 3 and Zen 4 for MI300 Data Center APU in 2023". AnandTech. Retrieved December 20, 2022.
  2. ↑ Smith, Ryan. "AMD Unveils CDNA GPU Architecture: A Dedicated GPU Architecture for Data Centers". www.anandtech.com. Retrieved September 20, 2022.
  3. ↑ "GPU Database: AMD Radeon Instinct MI100". TechPowerUp. Retrieved September 20, 2022.
  4. ↑ Smith, Ryan. "AMD Announces Instinct MI200 Accelerator Family: Taking Servers to Exascale and Beyond". www.anandtech.com. Retrieved September 21, 2022.
  5. ↑ Smith, Ryan. "AMD Releases Instinct MI210 Accelerator: CDNA 2 On a PCIe Card". www.anandtech.com. Retrieved September 21, 2022.
  6. 1 2 3 Smith, Ryan. "CES 2023: AMD Instinct MI300 Data Center APU Silicon In Hand - 146B Transistors, Shipping H2'23". www.anandtech.com. Retrieved January 22, 2023.
  7. ↑ Kennedy, Patrick (November 16, 2020). "AMD Instinct MI100 32GB CDNA GPU Launched". ServeTheHome. Retrieved September 22, 2022.
  8. 1 2 3 "AMD CDNA Whitepaper" (PDF). amd.com. March 5, 2020. Retrieved September 22, 2022.
  9. ↑ ""AMD Instinct MI100" Instruction Set Architecture, Reference Guide" (PDF). developer.amd.com. December 14, 2020. Retrieved September 22, 2022.
  10. ↑ Aaron Klotz (December 14, 2022). "Samsung Soups Up 96 AMD MI100 GPUs With Radical Computational Memory". Tom's Hardware. Retrieved December 23, 2022.
  11. ↑ "AMD Instinct MI100 Brochure" (PDF). AMD. Retrieved December 25, 2022.
  12. ↑ "AMD CDNA Whitepaper" (PDF). AMD. Retrieved December 25, 2022.
  13. ↑ Anton Shilov (November 17, 2021). "AMD's Instinct MI250X OAM Card Pictured: Aldebaran's Massive Die Revealed". Tom's Hardware. Retrieved November 20, 2022.
  14. 1 2 3 4 5 "Hot Chips 34 – AMD's Instinct MI200 Architecture". Chips and Cheese. September 18, 2022. Retrieved November 10, 2022.
  15. 1 2 3 4 "INTRODUCING AMD CDNA™ 2 ARCHITECTURE" (PDF). AMD.com. Retrieved November 20, 2022.
  16. ↑ ""AMD Instinct MI200" Instruction Set Architecture" (PDF). developer.amd.com. February 4, 2022. Retrieved October 11, 2022.
  17. 1 2 Paul Alcorn (January 5, 2023). "AMD Instinct MI300 Data Center APU Pictured Up Close: 13 Chiplets, 146 Billion Transistors". Tom's Hardware. Retrieved January 22, 2023.
  18. ↑ Oh, Nate (December 16, 2022). "Nvidia Formally Announced PCIe Tesla V100". AnandTech.
  19. ↑ "NVIDIA Tesla V100 PCIe 16GB". TechPowerUp.
  20. ↑ Smith, Ryan (December 19, 2022). "Nvidia Volta Unveiled". AnandTech.
  21. ↑ "NVIDIA Tesla V100 SXM3 32GB". TechPowerUp.
  22. ↑ Walton, Jarred (January 10, 2019). "Hands on with the AMD Radeon VII". PC Gamer.
  23. 1 2 "Next Horizon – David Wang Presentation" (PDF). AMD.
  24. ↑ "AMD Radeon Instinct MI50 Accelerator (16GB)". AMD.
  25. ↑ "AMD Radeon Instinct MI50 Accelerator (32GB)". AMD.
  26. ↑ "AMD Radeon Instinct MI50 Datasheet" (PDF). AMD.
  27. ↑ "AMD Radeon Instinct MI50 Specs". TechPowerUp. Retrieved May 27, 2022.
  28. ↑ "Radeon Instinct MI60". AMD. Archived from the original on November 22, 2018. Retrieved May 27, 2022.
  29. ↑ "AMD Radeon Instinct MI60 Datasheet" (PDF). AMD.
  30. ↑ "AMD Radeon Instinct MI60 Specs". TechPowerUp. Retrieved May 27, 2022.
  31. ↑ "Nvidia A100 Tensor Core GPU Archiecture" (PDF). Nvidia. Retrieved December 12, 2022.
  32. ↑ "Nvidia A100 PCIE 80 GB Specs". TechPowerUp. Retrieved December 12, 2022.
  33. ↑ "Nvidia A100 Tensor Core GPU Archiecture" (PDF). Nvidia. Retrieved December 12, 2022.
  34. ↑ "Nvidia A100 SXM4 80 GB Specs". TechPowerUp. Retrieved December 12, 2022.
  35. ↑ "AMD Instinct MI100 Brochure" (PDF). AMD. Retrieved December 25, 2022.
  36. ↑ "AMD CDNA Whitepaper" (PDF). AMD. Retrieved December 25, 2022.
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