Video Coding Engine

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Video Code Engine (VCE, was earlier referred to as Video Coding Engine, [1] Video Compression Engine [2] or Video Codec Engine [3] in official AMD documentation) is AMD's video encoding application-specific integrated circuit implementing the video codec H.264/MPEG-4 AVC. Since 2012 it was integrated into all of their GPUs and APUs except Oland.

Contents

VCE was introduced with the Radeon HD 7000 series on 22 December 2011. [4] [5] [6] VCE occupies a considerable amount of the die surface at the time of its introduction [7] and is not to be confused with AMD's Unified Video Decoder (UVD).

As of AMD Raven Ridge (released January 2018), UVD and VCE were succeeded by Video Core Next (VCN).

Overview

In "full-fixed mode" the entire computation is done by the fixed-function VCE unit. Full-fixed mode can be accessed through the OpenMAX IL API. AMD VCE fixed mode.svg
In "full-fixed mode" the entire computation is done by the fixed-function VCE unit. Full-fixed mode can be accessed through the OpenMAX IL API.
The entropy encoding block of the VCE ASIC is also separately accessible, enabling "hybrid mode". In "hybrid mode" most of the computation is done by the 3D engine of the GPU. Using AMD's Accelerated Parallel Programming SDK and OpenCL developers can create hybrid encoders that pair custom motion estimation, inverse discrete cosine transform and motion compensation with the hardware entropy encoding to achieve faster than real-time encoding. AMD VCE hybrid mode.svg
The entropy encoding block of the VCE ASIC is also separately accessible, enabling "hybrid mode". In "hybrid mode" most of the computation is done by the 3D engine of the GPU. Using AMD's Accelerated Parallel Programming SDK and OpenCL developers can create hybrid encoders that pair custom motion estimation, inverse discrete cosine transform and motion compensation with the hardware entropy encoding to achieve faster than real-time encoding.

The handling of video data involves computation of data compression algorithms and possibly of video processing algorithms. As the template compression methods shows, lossy video compression algorithms involve the steps: motion estimation (ME), discrete cosine transform (DCT), and entropy encoding (EC).

AMD Video Code Engine (VCE) is a full hardware implementation of the video codec H.264/MPEG-4 AVC. It is capable of delivering 1080p at 60 frames/sec. Because its entropy encoding block is also a separately accessible Video Codec Engine, it can be operated in two modes: full-fixed mode and hybrid mode. [8] [9]

By employing AMD APP SDK, available for Linux and Microsoft Windows, developers can create hybrid encoders that pair custom motion estimation, inverse discrete cosine transform and motion compensation with the hardware entropy encoding to achieve faster than real-time encoding. In hybrid mode, only the entropy encoding block of the VCE unit is used, while the remaining computation is offloaded to the 3D engine of the GPU, so the computing scales with the number of available compute units (CUs).

VCE 1.0

VCE [1] Version 1.0 supports H.264 YUV420 (I & P frames), H.264 SVC Temporal Encode VCE, and Display Encode Mode (DEM).

It can be found on:

VCE 2.0

Compared to the first version, VCE 2.0 adds H.264 YUV444 (I-Frames), B-frames for H.264 YUV420, and improvements to the DEM (Display Encode Mode), which results in a better encoding quality.

It can be found on:

VCE 3.0

Video Code Engine 3.0 (VCE 3.0) technology features a new high-quality video scaling and - since version 3.4 - High Efficiency Video Coding (HEVC/H.265). [10] [11]

It, together with UVD 6.0, can be found on 3rd generation of Graphics Core Next (GCN3) with "Tonga", "Fiji", "Iceland", and "Carrizo" (VCE 3.1) based graphics controller hardware, which is now used AMD Radeon Rx 300 series (Pirate Islands GPU family) and VCE 3.4 by actual AMD Radeon Rx 400 series and AMD Radeon 500 series (both Polaris GPU family).

VCE 3.0 removes support for H.264 B-frames. [12]

VCE 4.0

The Video Code Engine 4.0 encoder and UVD 7.0 decoder are included in the Vega-based GPUs. [13] [14]

VCE 4.1

AMD's Vega20 GPU, present in the Instinct Mi50, Instinct Mi60 and Radeon VII cards, include VCE 4.1 and two UVD 7.2 instances. [15] [16]

Feature overview

APUs

The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).

[  VisualEditor  ]
PlatformHigh, standard and low powerLow and ultra-low power
CodenameServerBasic Toronto
Micro Kyoto
DesktopPerformance Raphael Phoenix
Mainstream Llano Trinity Richland Kaveri Kaveri Refresh (Godavari) Carrizo Bristol Ridge Raven Ridge Picasso Renoir Cezanne
Entry
Basic Kabini Dalí
MobilePerformance Renoir Cezanne Rembrandt Dragon Range
Mainstream Llano Trinity Richland Kaveri Carrizo Bristol Ridge Raven Ridge Picasso Renoir
Lucienne 		Cezanne
Barceló 		Phoenix
Entry Dalí Mendocino
Basic Desna, Ontario, Zacate Kabini, Temash Beema, Mullins Carrizo-L Stoney Ridge Pollock
Embedded Trinity Bald Eagle Merlin Falcon,
Brown Falcon 		Great Horned Owl Grey Hawk Ontario, Zacate Kabini Steppe Eagle, Crowned Eagle,
LX-Family 		Prairie Falcon Banded Kestrel River Hawk
ReleasedAug 2011Oct 2012Jun 2013Jan 20142015Jun 2015Jun 2016Oct 2017Jan 2019Mar 2020Jan 2021Jan 2022Sep 2022Jan 2023Jan 2011May 2013Apr 2014May 2015Feb 2016Apr 2019Jul 2020Jun 2022Nov 2022
CPU microarchitecture K10 Piledriver Steamroller Excavator "Excavator+" [17] Zen Zen+ Zen 2 Zen 3 Zen 3+ Zen 4 Bobcat Jaguar Puma Puma+ [18] "Excavator+" Zen Zen+ "Zen 2+"
ISA x86-64 v1 x86-64 v2 x86-64 v3 x86-64 v4 x86-64 v1 x86-64 v2 x86-64 v3
Socket DesktopPerformance— AM5 ——
Mainstream— AM4 ——
Entry FM1 FM2 FM2+ FM2+ [lower-alpha 1] , AM4 AM4 —
Basic—— AM1 — FP5 —
Other FS1 FS1+, FP2 FP3 FP4 FP5 FP6 FP7 FL1FP7
FP7r2
FP8		 ? FT1 FT3 FT3b FP4 FP5 FT5 FP5 FT6
PCI Express version2.03.04.05.04.02.03.0
CXL ——
Fab. (nm) GF 32SHP
(HKMG SOI)		GF 28SHP
(HKMG bulk)		GF 14LPP
(FinFET bulk)		GF 12LP
(FinFET bulk)		 TSMC N7
(FinFET bulk)		TSMC N6
(FinFET bulk)		CCD: TSMC N5
(FinFET bulk)
cIOD: TSMC N6
(FinFET bulk)		TSMC 4nm
(FinFET bulk)		TSMC N40
(bulk)		TSMC N28
(HKMG bulk)		GF 28SHP
(HKMG bulk)		GF 14LPP
(FinFET bulk)		GF 12LP
(FinFET bulk)		TSMC N6
(FinFET bulk)
Die area (mm2)228246245245250210 [19] 156180210CCD: (2x) 70
cIOD: 122		17875 (+ 28 FCH)107 ?125149~100
Min TDP (W)3517121015105354.543.95106128
Max APU TDP (W)10095654517054182565415
Max stock APU base clock (GHz)33.84.14.13.73.83.63.73.84.03.34.74.31.752.222.23.22.61.23.352.8
Max APUs per node [lower-alpha 2] 11
Max core dies per CPU1211
Max CCX per core die1211
Max cores per CCX482424
Max CPU [lower-alpha 3] cores per APU481682424
Max threads per CPU core1212
Integer pipeline structure3+32+24+24+2+11+3+3+1+21+1+1+12+24+24+2+1
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHFYes check.svgYes check.svg
IOMMU [lower-alpha 4] —v2v1v2
BMI1, AES-NI, CLMUL, and F16C Yes check.svg—Yes check.svg
MOVBE—Yes check.svg
AVIC, BMI2, RDRAND, and MWAITX/MONITORX—Yes check.svg
SME [lower-alpha 5] , TSME [lower-alpha 5] , ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing—Yes check.svg—Yes check.svg
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT—Yes check.svg—Yes check.svg
MPK, VAES —Yes check.svg—
SGX ——
FPUs per core 10.5110.51
Pipes per FPU22
FPU pipe width128-bit256-bit80-bit128-bit256-bit
CPU instruction set SIMD level SSE4a [lower-alpha 6] AVX AVX2 AVX-512 SSSE3 AVX AVX2
3DNow! 3DNow!+ ——
PREFETCH/PREFETCHW Yes check.svgYes check.svg
GFNI —Yes check.svg—
AMX —
FMA4, LWP, TBM, and XOP —Yes check.svg——Yes check.svg—
FMA3 Yes check.svgYes check.svg
AMD XDNA —Yes check.svg—
L1 data cache per core (KiB)64163232
L1 data cache associativity (ways)2488
L1 instruction caches per core 10.5110.51
Max APU total L1 instruction cache (KiB)2561281922565122566412896128
L1 instruction cache associativity (ways)23482348
L2 caches per core 10.5110.51
Max APU total L2 cache (MiB)424161212
L2 cache associativity (ways)168168
Max on--die L3 cache per CCX (MiB)—41632—4
Max 3D V-Cache per CCD (MiB)—64——
Max total in-CCD L3 cache per APU (MiB)4816644
Max. total 3D V-Cache per APU (MiB)—64——
Max. board L3 cache per APU (MiB)——
Max total L3 cache per APU (MiB)48161284
APU L3 cache associativity (ways)1616
L3 cache scheme Victim Victim
Max. L4 cache ——
Max stock DRAM support DDR3-1866DDR3-2133DDR3-2133, DDR4-2400DDR4-2400DDR4-2933DDR4-3200, LPDDR4-4266 DDR5-4800, LPDDR5-6400 DDR5-5200 DDR5-5600, LPDDR5x-7500 DDR3L-1333DDR3L-1600DDR3L-1866DDR3-1866, DDR4-2400DDR4-2400DDR4-1600DDR4-3200LPDDR5-5500
Max DRAM channels per APU21212
Max stock DRAM bandwidth (GB/s) per APU29.86634.13238.40046.93268.256102.40083.200120.00010.66612.80014.93319.20038.40012.80051.20088.000
GPU microarchitecture TeraScale 2 (VLIW5) TeraScale 3 (VLIW4) GCN 2nd gen GCN 3rd gen GCN 5th gen [20] RDNA 2 RDNA 3 TeraScale 2 (VLIW5) GCN 2nd gen GCN 3rd gen [20] GCN 5th gen RDNA 2
GPU instruction set TeraScale instruction set GCN instruction set RDNA instruction set TeraScale instruction set GCN instruction set RDNA instruction set
Max stock GPU base clock (MHz)60080084486611081250140021002400400538600 ?847900120060013001900
Max stock GPU base GFLOPS [lower-alpha 7] 480614.4648.1886.71134.517601971.22150.43686.4102.486 ? ? ?345.6460.8230.41331.2486.4
3D engine [lower-alpha 8] Up to 400:20:8Up to 384:24:6Up to 512:32:8Up to 704:44:16 [21] Up to 512:32:8768:48:8128:8:480:8:4128:8:4Up to 192:12:8Up to 192:12:4192:12:4Up to 512:?:?128:?:?
IOMMUv1 IOMMUv2 IOMMUv1 ?IOMMUv2
Video decoder UVD 3.0 UVD 4.2 UVD 6.0 VCN 1.0 [22] VCN 2.1 [23] VCN 2.2 [23] VCN 3.1 ? UVD 3.0 UVD 4.0 UVD 4.2 UVD 6.0 UVD 6.3 VCN 1.0 VCN 3.1
Video encoder— VCE 1.0 VCE 2.0 VCE 3.1 — VCE 2.0 VCE 3.1
AMD Fluid MotionDark Red x.svgYes check.svgDark Red x.svgDark Red x.svgYes check.svgDark Red x.svg
GPU power saving PowerPlay PowerTune PowerPlay PowerTune [24]
TrueAudio —Yes check.svg [25]  ?—Yes check.svg
FreeSync 1
2		1
2
HDCP [lower-alpha 9]  ?1.42.22.3 ?1.42.22.3
PlayReady [lower-alpha 9] —3.0 not yet—3.0 not yet
Supported displays [lower-alpha 10] 2–32–433 (desktop)
4 (mobile, embedded)		42344
/drm/radeon [lower-alpha 11] [27] [28] Yes check.svg—Yes check.svg—
/drm/amdgpu [lower-alpha 11] [29] —Yes check.svg [30] —Yes check.svg [30]
  1. ↑ For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
  2. ↑ A PC would be one node.
  3. ↑ An APU combines a CPU and a GPU. Both have cores.
  4. ↑ Requires firmware support.
  5. 1 2 Requires firmware support.
  6. ↑ No SSE4. No SSSE3.
  7. ↑ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  8. ↑ Unified shaders  : texture mapping units  : render output units
  9. 1 2 To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
  10. ↑ To feed more than two displays, the additional panels must have native DisplayPort support. [26] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
  11. 1 2 DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

GPUs

The following table shows features of AMD/ATI's GPUs (see also: List of AMD graphics processing units).

[  VisualEditor  ]
Name of GPU series Wonder Mach 3D Rage Rage Pro Rage 128 R100 R200 R300 R400 R500 R600 RV670 R700 Evergreen Northern
Islands 		Southern
Islands 		Sea
Islands 		Volcanic
Islands 		Arctic
Islands/Polaris 		Vega Navi 1x Navi 2x Navi 3x
Released19861991Apr
1996		Mar
1997		Aug
1998		Apr
2000		Aug
2001		Sep
2002		May
2004		Oct
2005		May
2007		Nov
2007		Jun
2008		Sep
2009		Oct
2010		Jan
2012		Sep
2013		Jun
2015		Jun 2016, Apr 2017, Aug 2019Jun 2017, Feb 2019Jul
2019		Nov
2020		Dec
2022
Marketing Name WonderMach3D
Rage		Rage
Pro		Rage
128		Radeon
7000		Radeon
8000		Radeon
9000		Radeon
X700/X800		Radeon
X1000		Radeon
HD 2000		Radeon
HD 3000		Radeon
HD 4000		Radeon
HD 5000		Radeon
HD 6000		Radeon
HD 7000		Radeon
200		Radeon
300		Radeon
400/500/600		Radeon
RX Vega, Radeon VII		Radeon
RX 5000		Radeon
RX 6000		Radeon
RX 7000
AMD supportDark Red x.svgYes check.svg
Kind2D3D
Instruction set architecture Not publicly known TeraScale instruction set GCN instruction set RDNA instruction set
Microarchitecture TeraScale 1
(VLIW) 		TeraScale 2
(VLIW5)
TeraScale 2
(VLIW5)
up to 68xx		 TeraScale 3
(VLIW4)
in 69xx [31] [32]
GCN 1st
gen 		GCN 2nd
gen 		GCN 3rd
gen 		GCN 4th
gen 		GCN 5th
gen 		RDNA RDNA 2 RDNA 3
TypeFixed pipeline [lower-alpha 1] Programmable pixel & vertex pipelines Unified shader model
Direct3D —5.06.07.08.19.0
11 (9_2)		9.0b
11 (9_2)		9.0c
11 (9_3)		10.0
11 (10_0)		10.1
11 (10_1)		11 (11_0)11 (11_1)
12 (11_1)		11 (12_0)
12 (12_0)		11 (12_1)
12 (12_1)		11 (12_1)
12 (12_2)
Shader model —1.42.0+2.0b3.04.04.15.05.15.1
6.5		6.7
OpenGL —1.11.21.32.1 [lower-alpha 2] [33] 3.3 4.5 (on Linux: 4.5 (Mesa 3D 21.0)) [34] [35] [36] [lower-alpha 3] 4.6 (on Linux: 4.6 (Mesa 3D 20.0))
Vulkan —1.0
(Win 7+ or Mesa 17+)		1.2 (Adrenalin 20.1.2, Linux Mesa 3D 20.0)1.3 (Adrenalin 22.1.2, Mesa 22.0)
OpenCL — Close to Metal 1.1 (no Mesa 3D support)1.2+ (on Linux: 1.1+ (no Image support on clover, with by rustiCL) with Mesa 3D, 1.2+ on GCN 1.Gen)2.0+ (Adrenalin driver on Win7+)
(on Linux ROCM, Linux Mesa 3D 1.2+ (no Image support in clover, but in rustiCL with Mesa 3D, 2.0+ and 3.0 with AMD drivers or AMD ROCm), 5th gen: 2.2 win 10+ and Linux RocM 5.0+		2.2+ and 3.0 windows 8.1+ and Linux ROCM 5.0+ (Mesa 3D rustiCL 1.2+ and 3.0 (2.1+ and 2.2+ wip)) [37] [38] [39]
HSA / ROCm —Yes check.svg ?
Video decoding ASIC — Avivo/UVD UVD+ UVD 2 UVD 2.2 UVD 3 UVD 4 UVD 4.2 UVD 5.0 or 6.0 UVD 6.3 UVD 7 [13] [lower-alpha 4] VCN 2.0 [13] [lower-alpha 4] VCN 3.0 [40] VCN 4.0
Video encoding ASIC — VCE 1.0 VCE 2.0 VCE 3.0 or 3.1 VCE 3.4 VCE 4.0 [13] [lower-alpha 4]
Fluid Motion [lower-alpha 5] Dark Red x.svgYes check.svgDark Red x.svg ?
Power saving ? PowerPlay PowerTune PowerTune & ZeroCore Power  ?
TrueAudio —Via dedicated DSP Via shaders
FreeSync —1
2
HDCP [lower-alpha 6]  ?1.42.22.3 [41]
PlayReady [lower-alpha 6] —3.0Dark Red x.svg3.0
Supported displays [lower-alpha 7] 1–222–6 ?
Max. resolution  ?2–6 ×
2560×1600		2–6 ×
4096×2160 @ 30 Hz		2–6 ×
5120×2880 @ 60 Hz		3 ×
7680×4320 @ 60 Hz [42]
7680×4320 @ 60 Hz PowerColor 		7680x4320

@165 HZ

/drm/radeon [lower-alpha 8] Yes check.svg—
/drm/amdgpu [lower-alpha 8] —Experimental [43] Optional [44] Yes check.svg
  1. ↑ The Radeon 100 Series has programmable pixel shaders, but do not fully comply with DirectX 8 or Pixel Shader 1.0. See article on R100's pixel shaders.
  2. ↑ R300, R400 and R500 based cards do not fully comply with OpenGL 2+ as the hardware does not support all types of non-power of two (NPOT) textures.
  3. ↑ OpenGL 4+ compliance requires supporting FP64 shaders and these are emulated on some TeraScale chips using 32-bit hardware.
  4. 1 2 3 The UVD and VCE were replaced by the Video Core Next (VCN) ASIC in the Raven Ridge APU implementation of Vega.
  5. ↑ Video processing for video frame rate interpolation technique. In Windows it works as a DirectShow filter in your player. In Linux, there is no support on the part of drivers and / or community.
  6. 1 2 To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
  7. ↑ More displays may be supported with native DisplayPort connections, or splitting the maximum resolution between multiple monitors with active converters.
  8. 1 2 DRM (Direct Rendering Manager) is a component of the Linux kernel. AMDgpu is the Linux kernel module. Support in this table refers to the most current version.

Operating system support

The VCE SIP core needs to be supported by the device driver. The device driver provides one or multiple interfaces, e. g. OpenMAX IL. One of these interfaces is then used by end-user software, like GStreamer or HandBrake (HandBrake rejected VCE support in December 2016, [45] but added it in December 2018 [46] ), to access the VCE hardware and make use of it.

AMD's proprietary device driver AMD Catalyst is available for multiple operating systems and support for VCE was added to it[ citation needed ]. Additionally, a free device driver is available. This driver also supports the VCE hardware.

Linux

Support for the VCE ASIC is contained in the Linux kernel device driver amdgpu. Linux AMD graphics stack.svg
Support for the VCE ASIC is contained in the Linux kernel device driver amdgpu.

Windows

The software "MediaShow Espresso Video Transcoding" seems to utilize VCE and UVD to the fullest extent possible. [51]

XSplit Broadcaster supports VCE from version 1.3. [52]

Open Broadcaster Software (OBS Studio) supports VCE for recording and streaming. The original Open Broadcaster Software (OBS) requires a fork build in order to enable VCE. [53]

AMD Radeon Software supports VCE with built in game capture ("Radeon ReLive") and use AMD AMF/VCE on APU or Radeon Graphics card to reduce FPS drop when capturing game or video content. [54]

HandBrake added Video Coding Engine support in version 1.2.0 in December 2018. [46]

Successor

The VCE was succeeded by AMD Video Core Next in the Raven Ridge series of APUs released in October 2017. The VCN combines both encode (VCE) and decode (UVD). [55]

See also

Video hardware technologies

AMD

Others

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References

  1. 1 2 "Introducing the Video Coding Engine (VCE) - AMD". developer.amd.com. Archived from the original on 4 June 2016. Retrieved 15 January 2022.
  2. ↑ "Product brief". amd.com.
  3. ↑ "Updates" (PDF). amd.com.
  4. ↑ "White Paper AMD UnifiedVideoDecoder (UVD)" (PDF). 2012-06-15. Retrieved 2017-05-20.
  5. ↑ "AnandTech Portal | AMD Radeon HD 7970 Review: 28nm And Graphics Core Next, Together As One". Anandtech.com. Retrieved 2014-03-27.
  6. ↑ "AMD's Radeon HD 7970 graphics processor - The Tech Report - Page 5". The Tech Report. 3 January 2012. Retrieved 2014-03-27.
  7. ↑ "AMD A-Series APU block diagram". 2011-06-30. Retrieved 2015-01-22.
  8. ↑ "Video & Movies: The Video Codec Engine, UVD3, & Steady Video 2.0". AnandTech. December 22, 2011. Retrieved 2017-05-20.
  9. ↑ "Radeon HD 8900 Specs". AMD. Retrieved 2016-07-18.
  10. ↑ "Mailing Lists". lists.freedesktop.org. 4 June 2015. Retrieved 25 September 2023.
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  12. ↑ "Video Encode API: BFrames not supported on RX 4xx? · Issue #8 · GPUOpen-LibrariesAndSDKs/AMF". GitHub.
  13. 1 2 3 4 Killian, Zak (March 22, 2017). "AMD publishes patches for Vega support on Linux". Tech Report. Retrieved March 23, 2017.
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  15. ↑ Deucher, Alex (15 May 2018). "[PATCH 50/57] drm/amdgpu/vg20:Enable the 2nd instance IRQ for uvd 7.2" . Retrieved 2019-01-13.
  16. ↑ Deucher, Alex (15 May 2018). "[PATCH 42/57] drm/amd/include/vg20: adjust VCE_BASE to reuse vce 4.0 header files" . Retrieved 2019-01-13.
  17. ↑ "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020.
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  19. ↑ "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
  20. 1 2 "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
  21. ↑ Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
  22. ↑ Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
  23. 1 2 "AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. Aug 12, 2021. Retrieved August 25, 2021.
  24. ↑ Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016
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  28. ↑ "Radeon feature matrix". freedesktop.org . Retrieved 10 January 2016.
  29. ↑ Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.
  30. 1 2 Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.
  31. ↑ "AMD Radeon HD 6900 (AMD Cayman) series graphics cards". HWlab. hw-lab.com. December 19, 2010. Archived from the original on August 23, 2022. Retrieved August 23, 2022. New VLIW4 architecture of stream processors allowed to save area of each SIMD by 10%, while performing the same compared to previous VLIW5 architecture
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  33. ↑ "NPOT Texture (OpenGL Wiki)". Khronos Group. Retrieved February 10, 2021.
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  44. ↑ "AMDGPU" . Retrieved December 29, 2023.
  45. ↑ "HandBrake rejected VCE pull request". GitHub . 2016-12-08. Retrieved 2017-08-15.
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  47. ↑ König, Christian (4 February 2014). "initial VCE support". mesa-dev (Mailing list). Retrieved 28 November 2015.
  48. ↑ König, Christian (24 October 2013). "OpenMAX state tracker". mesa-dev (Mailing list). Retrieved 28 November 2015.
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  50. ↑ "st/omx/enc: implement h264 level support". 2014-06-12. Retrieved 2017-05-20.
  51. ↑ "MediaShow Espresso Video Transcoding Benchmark". 2014-01-14. Retrieved 2017-05-20.
  52. ↑ "XSplit Broadcaster 1.3 maintenance update includes mainly performance enhancements and maintenance fixes including such noteworthy features such as support for AMD's VCE H.264 hardware encoder". Archived from the original on 2014-07-22.
  53. ↑ "OBS branch with AMD VCE support". May 2, 2014. Retrieved 2017-05-20.
  54. ↑ "Radeon Software Crimson ReLive Edition 16.12.1 Release Notes" . Retrieved 2017-05-20.
  55. ↑ Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands In Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
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