Type | PGA-ZIF |
---|---|
Chip form factors | PGA |
Contacts | 905 |
FSB protocol | Unified Media Interface (UMI) |
FSB frequency | 100 MHz System clock UMI up to 5,2 GT/s |
Processors | early A-series APUs |
Successor | FM2 |
This article is part of the CPU socket series |
Socket FM1 is a CPU socket for desktop computers used by AMD early A-series APUs ("Llano") processors and Llano-derived Athlon II processors. It was released in July 2011. Its direct successors are Socket FM2 (September 2012) and Socket FM2+ (January 2014), while Socket AM1 (January 2014) is targeting low-power SoCs.
For available chipsets consult Fusion controller hubs (FCH).
APU's using Socket FM1 are AMD's Lynx platform.
Please consult List of AMD accelerated processing units for concrete product denominations.
The following table shows features of AMD's APUs (see also: List of AMD accelerated processing units).
Codename | Server | Basic | Toronto | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Micro | Kyoto | |||||||||||||||||
Desktop | Mainstream | Carrizo | Bristol Ridge | Raven Ridge | Picasso | |||||||||||||
Entry | Llano | Trinity | Richland | Kaveri | ||||||||||||||
Basic | Kabini | |||||||||||||||||
Mobile | Performance | Renoir | ||||||||||||||||
Mainstream | Llano | Trinity | Richland | Kaveri | Carrizo | Bristol Ridge | Raven Ridge | Picasso | ||||||||||
Entry | Dalí | |||||||||||||||||
Basic | Desna, Ontario, Zacate | Kabini, Temash | Beema, Mullins | Carrizo-L | Stoney Ridge | |||||||||||||
Embedded | Trinity | Bald Eagle | Merlin Falcon, Brown Falcon | Great Horned Owl | Ontario, Zacate | Kabini | Steppe Eagle, Crowned Eagle, LX-Family | Prairie Falcon | Banded Kestrel | |||||||||
Platform | High, standard and low power | Low and ultra-low power | ||||||||||||||||
Released | Aug 2011 | Oct 2012 | Jun 2013 | Jan 2014 | Jun 2015 | Jun 2016 | Oct 2017 | Jan 2019 | Mar 2020 | Jan 2011 | May 2013 | Apr 2014 | May 2015 | Feb 2016 | Apr 2019 | |||
CPU microarchitecture | K10 | Piledriver | Steamroller | Excavator | "Excavator+" [1] | Zen | Zen+ | Zen 2 | Bobcat | Jaguar | Puma | Puma+ [2] | "Excavator+" | Zen | ||||
ISA | x86-64 | x86-64 | ||||||||||||||||
Socket | Desktop | High-end | N/A | N/A | ||||||||||||||
Mainstream | N/A | AM4 | ||||||||||||||||
Entry | FM1 | FM2 | FM2+ [lower-alpha 1] | N/A | ||||||||||||||
Basic | N/A | N/A | AM1 | N/A | ||||||||||||||
Other | FS1 | FS1+, FP2 | FP3 | FP4 | FP5 | FP6 | FT1 | FT3 | FT3b | FP4 | FP5 | |||||||
PCI Express version | 2.0 | 3.0 | 2.0 | 3.0 | ||||||||||||||
Fab. (nm) | GF 32SHP (HKMG SOI) | GF 28SHP (HKMG bulk) | GF 14LPP (FinFET bulk) | GF 12LP (FinFET bulk) | TSMC N7 (FinFET bulk) | TSMC N40 (bulk) | TSMC N28 (HKMG bulk) | GF 28SHP (HKMG bulk) | GF 14LPP (FinFET bulk) | |||||||||
die area (mm2) | 228 | 246 | 245 | 245 | 250 | 210 [3] | 156 | 75 (+ 28 FCH) | 107 | ? | 125 | |||||||
Min TDP | 35W | 17W | 12W | 10W | 4.5W | 4W | 3.95W | 10W | 6W | |||||||||
Max APU TDP | 100W | 95W | 65W | 54W | 18W | 25W | ||||||||||||
Max stock APU base clock (GHz) | 3 | 3.8 | 4.1 | 3.7 | 3.8 | 3.6 | 3.7 | 3.3 | 1.75 | 2.2 | 2 | 2.2 | 3.2 | 3.3 | ||||
Max APUs per node [lower-alpha 2] | 1 | 1 | ||||||||||||||||
Max CPU [lower-alpha 3] cores per APU | 4 | 8 | 2 | 4 | 2 | |||||||||||||
Max threads per CPU core | 1 | 2 | 1 | 2 | ||||||||||||||
Integer structure | 3+3 | 2+2 | 4+2 | 4+2+1 | 1+1+1+1 | 2+2 | 4+2 | |||||||||||
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF | ||||||||||||||||||
IOMMU [lower-alpha 4] | N/A | |||||||||||||||||
BMI1, AES-NI, CLMUL, and F16C | N/A | |||||||||||||||||
MOVBE | N/A | |||||||||||||||||
AVIC, BMI2 and RDRAND | N/A | |||||||||||||||||
ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERO | N/A | N/A | ||||||||||||||||
WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMIT | N/A | N/A | ||||||||||||||||
FPUs per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | ||||||||||||
Pipes per FPU | 2 | 2 | ||||||||||||||||
FPU pipe width | 128-bit | 256-bit | 80-bit | 128-bit | ||||||||||||||
CPU instruction set SIMD level | SSE4a [lower-alpha 5] | AVX | AVX2 | SSSE3 | AVX | AVX2 | ||||||||||||
3DNow! | 3DNow!+ | N/A | N/A | |||||||||||||||
PREFETCH/PREFETCHW | ||||||||||||||||||
FMA4, LWP, TBM, and XOP | N/A | N/A | N/A | N/A | ||||||||||||||
FMA3 | ||||||||||||||||||
L1 data cache per core (KiB) | 64 | 16 | 32 | 32 | ||||||||||||||
L1 data cache associativity (ways) | 2 | 4 | 8 | 8 | ||||||||||||||
L1 instruction caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | ||||||||||||
Max APU total L1 instruction cache (KiB) | 256 | 128 | 192 | 256 | 64 | 128 | 96 | 128 | ||||||||||
L1 instruction cache associativity (ways) | 2 | 3 | 4 | 8 | 2 | 3 | 4 | |||||||||||
L2 caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | ||||||||||||
Max APU total L2 cache (MiB) | 4 | 2 | 4 | 1 | 2 | 1 | ||||||||||||
L2 cache associativity (ways) | 16 | 8 | 16 | 8 | ||||||||||||||
APU total L3 cache (MiB) | N/A | 4 | 8 | N/A | 4 | |||||||||||||
APU L3 cache associativity (ways) | 16 | 16 | ||||||||||||||||
L3 cache scheme | victim | N/A | victim | victim | ||||||||||||||
Max stock DRAM support | DDR3-1866 | DDR3-2133 | DDR3-2133, DDR4-2400 | DDR4-2400 | DDR4-2933 | DDR4-3200, LPDDR4-4266 | DDR3L-1333 | DDR3L-1600 | DDR3L-1866 | DDR3-1866, DDR4-2400 | DDR4-2400 | |||||||
Max DRAM channels per APU | 2 | 1 | 2 | |||||||||||||||
Max stock DRAM bandwidth (GB/s) per APU | 29.866 | 34.132 | 38.400 | 46.932 | 68.256 | 10.666 | 12.800 | 14.933 | 19.200 | 38.400 | ||||||||
GPU microarchitecture | TeraScale 2 (VLIW5) | TeraScale 3 (VLIW4) | GCN 2nd gen | GCN 3rd gen | GCN 5th gen [4] | TeraScale 2 (VLIW5) | GCN 2nd gen | GCN 3rd gen [4] | GCN 5th gen | |||||||||
GPU instruction set | TeraScale instruction set | GCN instruction set | TeraScale instruction set | GCN instruction set | ||||||||||||||
Max stock GPU base clock (MHz) | 600 | 800 | 844 | 866 | 1108 | 1250 | 1400 | 1750 | 538 | 600 | ? | 847 | 900 | 1200 | ||||
Max stock GPU base GFLOPS [lower-alpha 6] | 480 | 614.4 | 648.1 | 886.7 | 1134.5 | 1760 | 1971.2 | 1792 | 86 | ? | ? | ? | 345.6 | 460.8 | ||||
3D engine [lower-alpha 7] | Up to 400:20:8 | Up to 384:24:6 | Up to 512:32:8 | Up to 704:44:16 [5] | Up to 512:?:? | 80:8:4 | 128:8:4 | Up to 192:?:? | Up to 192:?:? | |||||||||
IOMMUv1 | IOMMUv2 | IOMMUv1 | ? | IOMMUv2 | ||||||||||||||
Video decoder | UVD 3.0 | UVD 4.2 | UVD 6.0 | VCN 1.0 [6] | UVD 3.0 | UVD 4.0 | UVD 4.2 | UVD 6.0 | UVD 6.3 | VCN 1.0 | ||||||||
Video encoder | N/A | VCE 1.0 | VCE 2.0 | VCE 3.1 | N/A | VCE 2.0 | VCE 3.1 | |||||||||||
GPU power saving | PowerPlay | PowerTune | PowerPlay | PowerTune [7] | ||||||||||||||
TrueAudio | N/A | N/A | ||||||||||||||||
FreeSync | 1 2 | 1 2 | ||||||||||||||||
HDCP [lower-alpha 8] | ? | 1.4 | 1.4 2.2 | ? | 1.4 | 1.4 2.2 | ||||||||||||
PlayReady [lower-alpha 8] | N/A | 3.0 not yet | N/A | 3.0 not yet | ||||||||||||||
Supported displays [lower-alpha 9] | 2–3 | 2–4 | 3 | 3 (desktop) 4 (mobile, embedded) | 4 | 2 | 3 | 4 | ||||||||||
/drm/radeon [lower-alpha 10] [10] [11] | N/A | N/A | ||||||||||||||||
/drm/amdgpu [lower-alpha 10] [12] | N/A | N/A |
Advanced Micro Devices, Inc. (AMD) is a multinational semiconductor company based in Santa Clara County, California that develops computer processors and related technologies for business and consumer markets. While initially it manufactured its own processors, the company later outsourced its manufacturing, a practice known as going fabless, after GlobalFoundries was spun off in 2009. AMD's main products include microprocessors, motherboard chipsets, embedded processors and graphics processors for servers, workstations, personal computers and embedded system applications.
The AMD Accelerated Processing Unit (APU), formerly known as Fusion, is the marketing term for a series of 64-bit microprocessors from Advanced Micro Devices (AMD), designed to act as a central processing unit (CPU) and graphics processing unit (GPU) on a single die. APUs are general purpose processors that feature nearly discrete integrated graphics processors (IGPs), which generally are a class above what would normally be termed as "integrated" graphics.
Unified Video Decoder (UVD), previously called Universal Video Decoder, is the name given to AMD's dedicated video decoding ASIC. There are multiple versions implementing a multitude of video codecs, such as H.264 and VC-1.
AMD PowerPlay is the brand name for a set of technologies for the reduction of the energy consumption implemented in several of AMD's graphics processing units and APUs supported by their proprietary graphics device driver "Catalyst". AMD PowerPlay is also implemented into ATI/AMD chipsets which integrated graphics and into AMD's Imageon handheld chipset, that was sold to Qualcomm in 2008.
The Socket FS1 is for notebooks using AMD APU processors codenamed Llano, Trinity and Richland.
Socket FM2 is a CPU socket used by AMD's desktop Trinity and Richland APUs to connect to the motherboard as well as Athlon X2 and Athlon X4 processors based on them. FM2 was launched on September 27, 2012. Motherboards which feature the at the time new FM2 CPU socket also utilize AMD's at the time new A85X chipset.
Heterogeneous System Architecture (HSA) is a cross-vendor set of specifications that allow for the integration of central processing units and graphics processors on the same bus, with shared memory and tasks. The HSA is being developed by the HSA Foundation, which includes AMD and ARM. The platform's stated aim is to reduce communication latency between CPUs, GPUs and other compute devices, and make these various devices more compatible from a programmer's perspective, relieving the programmer of the task of planning the moving of data between devices' disjoint memories.
AMD Excavator Family 15h is a microarchitecture developed by AMD to succeed Steamroller Family 15h for use in AMD APU processors and normal CPUs. On October 12, 2011, AMD revealed Excavator to be the code name for the fourth-generation Bulldozer-derived core.
Socket FM2+ (FM2b) is a CPU socket used by AMD's desktop "Kaveri" APUs (Steamroller-based) and Godavari APUs (Steamroller-based) to connect to the motherboard. The FM2+ has a slightly different pin configuration to Socket FM2 with two additional pin sockets. Socket FM2+ APUs are not compatible with Socket FM2 motherboards due to the aforementioned additional pins. However, socket FM2 APUs such as "Richland" and "Trinity" are compatible with the FM2+ socket.
Video Code Engine is AMD's video encoding ASIC implementing the video codec H.264/MPEG-4 AVC. Since 2012 it is integrated into all of their GPUs and APUs except Oland.
AMD Eyefinity is a brand name for AMD video card products that support multi-monitor setups by integrating multiple display controllers on one GPU. AMD Eyefinity was introduced with the Radeon HD 5000 Series "Evergreen" in September 2009 and has been available on APUs and professional-grade graphics cards branded AMD FirePro as well.
AMD's Socket FT3 or BGA-769 targets mobile devices and was designed for APUs codenamed Kabini and Temash, Beema and Mullins.
The Socket FT1 or BGA413 is a CPU socket released in January 2011 from AMD for its APUs codenamed Desna, Ontario, Zacate and Hondo. The uber name is "Brazos".
The Socket FP2 or µBGA-827 is a CPU socket for notebooks that was released in May 2012 by AMD with its APU processors codenamed Trinity and Richland.
The Socket FP3 or µBGA906 is a CPU socket for laptops that was released in June 2014 by AMD with its mobility APU products codenamed Kaveri.
AMD PowerTune is a series of dynamic frequency scaling technologies built into some AMD GPUs and APUs that allow the clock speed of the processor to be dynamically changed by software. This allows the processor to meet the instantaneous performance needs of the operation being performed, while minimizing power draw, heat generation and noise avoidance. AMD PowerTune aims to solve thermal design power and performance constraints.
Ryzen is a brand of x86-64 microprocessors designed and marketed by Advanced Micro Devices, Inc. (AMD) for desktop, mobile and embedded platforms based on the Zen microarchitecture and its successors. It consists of central processing units marketed for mainstream, enthusiast and workstation segments and accelerated processing units (APUs) marketed for mainstream and entry-level segments and embedded applications. Ryzen is especially significant for AMD, since it is a completely new design, and since it marks the corporation's return to the high end desktop CPU market. AMD's competitor Intel has controlled this section of the market for almost ten years, back when Intel released the Conroe/Core microarchitecture, which overtook AMD's Athlon 64 as the cutting edge of performance in the market.
The Radeon RX Vega series is a series of graphics processors developed by AMD. These GPUs use the Graphics Core Next (GCN) 5th generation architecture, codenamed Vega, and are manufactured on 14 nm FinFET technology, developed by Samsung Electronics and licensed to GlobalFoundries. The series consists of desktop graphics cards and APUs aimed at desktops, mobile devices, and embedded applications.
This electronics-related article is a stub. You can help Wikipedia by expanding it. |