Socket FT3

Last updated
Socket FT3
Type BGA
Chip form factors?
Contacts769
Processorsmobile APU products (Kabini and Temash, Beema and Mullins)
This article is part of the CPU socket series

AMD's Socket FT3 or BGA-769 targets mobile devices and was designed for APUs codenamed Kabini and Temash, Beema and Mullins (Socket FT3b).

Contents

"Kabini"- and "Temash"-branded products combine Jaguar with Islands (GCN), UVD 3 and VCE 2.0 video acceleration and AMD Eyefinity-based multi-monitor support of maximum two monitors.

"Beema"- and "Mullins"-branded products combine Puma with AMD Radeon Rx 200 Series (GCN), UVD 3 and VCE 2.0 video acceleration and AMD Eyefinity-based multi-monitor support of maximum two monitors.

Its desktop counterpart is Socket AM1.

Feature overview for AMD APUs

The following table shows features of AMD's APUs (see also: List of AMD accelerated processing units).

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CodenameServerBasic Toronto
Micro Kyoto
DesktopMainstream Carrizo Bristol Ridge Raven Ridge Picasso
Entry Llano Trinity Richland Kaveri
Basic Kabini
MobilePerformance Renoir
Mainstream Llano Trinity Richland Kaveri Carrizo Bristol Ridge Raven Ridge Picasso
Entry Dalí
Basic Desna, Ontario, Zacate Kabini, Temash Beema, Mullins Carrizo-L Stoney Ridge
Embedded Trinity Bald Eagle Merlin Falcon,
Brown Falcon 		Great Horned Owl Ontario, Zacate Kabini Steppe Eagle, Crowned Eagle,
LX-Family 		Prairie Falcon Banded Kestrel
PlatformHigh, standard and low powerLow and ultra-low power
ReleasedAug 2011Oct 2012Jun 2013Jan 2014Jun 2015Jun 2016Oct 2017Jan 2019Mar 2020Jan 2011May 2013Apr 2014May 2015Feb 2016Apr 2019
CPU microarchitecture K10 Piledriver Steamroller Excavator "Excavator+" [1] Zen Zen+ Zen 2 Bobcat Jaguar Puma Puma+ [2] "Excavator+" Zen
ISA x86-64 x86-64
Socket DesktopHigh-endN/AN/A
MainstreamN/A AM4
Entry FM1 FM2 FM2+ [lower-alpha 1] N/A
BasicN/AN/A AM1 N/A
Other FS1 FS1+, FP2 FP3 FP4 FP5 FP6 FT1 FT3 FT3b FP4 FP5
PCI Express version2.03.02.03.0
Fab. (nm) GF 32SHP
(HKMG SOI)		GF 28SHP
(HKMG bulk)		GF 14LPP
(FinFET bulk)		GF 12LP
(FinFET bulk)		 TSMC N7
(FinFET bulk)		TSMC N40
(bulk)		TSMC N28
(HKMG bulk)		GF 28SHP
(HKMG bulk)		GF 14LPP
(FinFET bulk)
die area (mm2)228246245245250210 [3] 15675 (+ 28 FCH)107?125
Min TDP 35W17W12W10W4.5W4W3.95W10W6W
Max APU TDP 100W95W65W54W18W25W
Max stock APU base clock (GHz)33.84.13.73.83.63.73.31.752.222.23.23.3
Max APUs per node [lower-alpha 2] 11
Max CPU [lower-alpha 3] cores per APU48242
Max threads per CPU core1212
Integer structure3+32+24+24+2+11+1+1+12+24+2
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHFGreen check.svgGreen check.svg
IOMMU [lower-alpha 4] N/AGreen check.svg
BMI1, AES-NI, CLMUL, and F16C N/AGreen check.svg
MOVBEN/AGreen check.svg
AVIC, BMI2 and RDRAND N/AGreen check.svg
ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERON/AGreen check.svgN/AGreen check.svg
WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMITN/AGreen check.svgN/A
FPUs per core 10.5110.51
Pipes per FPU22
FPU pipe width128-bit256-bit80-bit128-bit
CPU instruction set SIMD level SSE4a [lower-alpha 5] AVX AVX2 SSSE3 AVX AVX2
3DNow! 3DNow!+ N/AN/A
PREFETCH/PREFETCHW Green check.svgGreen check.svg
FMA4, LWP, TBM, and XOP N/AGreen check.svgN/AN/AGreen check.svgN/A
FMA3 Green check.svgGreen check.svg
L1 data cache per core (KiB)64163232
L1 data cache associativity (ways)2488
L1 instruction caches per core 10.5110.51
Max APU total L1 instruction cache (KiB)2561281922566412896128
L1 instruction cache associativity (ways)2348234
L2 caches per core 10.5110.51
Max APU total L2 cache (MiB)424121
L2 cache associativity (ways)168168
APU total L3 cache (MiB)N/A48N/A4
APU L3 cache associativity (ways)1616
L3 cache scheme victim N/Avictimvictim
Max stock DRAM support DDR3-1866 DDR3-2133 DDR3-2133, DDR4-2400 DDR4-2400 DDR4-2933 DDR4-3200, LPDDR4-4266 DDR3L-1333 DDR3L-1600 DDR3L-1866 DDR3-1866, DDR4-2400 DDR4-2400
Max DRAM channels per APU212
Max stock DRAM bandwidth (GB/s) per APU29.86634.13238.40046.93268.25610.66612.80014.93319.20038.400
GPU microarchitecture TeraScale 2 (VLIW5) TeraScale 3 (VLIW4) GCN 2nd gen GCN 3rd gen GCN 5th gen [4] TeraScale 2 (VLIW5) GCN 2nd gen GCN 3rd gen [4] GCN 5th gen
GPU instruction set TeraScale instruction set GCN instruction set TeraScale instruction set GCN instruction set
Max stock GPU base clock (MHz)6008008448661108125014001750538600?8479001200
Max stock GPU base GFLOPS [lower-alpha 6] 480614.4648.1886.71134.517601971.2179286???345.6460.8
3D engine [lower-alpha 7] Up to 400:20:8Up to 384:24:6Up to 512:32:8Up to 704:44:16 [5] Up to 512:?:?80:8:4128:8:4Up to 192:?:?Up to 192:?:?
IOMMUv1 IOMMUv2 IOMMUv1?IOMMUv2
Video decoder UVD 3.0 UVD 4.2 UVD 6.0 VCN 1.0 [6] UVD 3.0 UVD 4.0 UVD 4.2 UVD 6.0 UVD 6.3 VCN 1.0
Video encoderN/A VCE 1.0 VCE 2.0 VCE 3.1 N/A VCE 2.0 VCE 3.1
GPU power saving PowerPlay PowerTune PowerPlay PowerTune [7]
TrueAudio N/AGreen check.svg [8] N/AGreen check.svg
FreeSync 1
2		1
2
HDCP [lower-alpha 8] ?1.41.4
2.2		?1.41.4
2.2
PlayReady [lower-alpha 8] N/A3.0 not yetN/A3.0 not yet
Supported displays [lower-alpha 9] 2–32–433 (desktop)
4 (mobile, embedded)		4234
/drm/radeon [lower-alpha 10] [10] [11] Green check.svgN/AGreen check.svgN/A
/drm/amdgpu [lower-alpha 10] [12] N/AGreen check.svg [13] Green check.svgN/AGreen check.svg [13] Green check.svg
  1. ↑ APU models: A8-7680, A6-7480. CPU only: Athlon X4 845.
  2. ↑ A PC would be one node.
  3. ↑ An APU combines a CPU and a GPU. Both have cores.
  4. ↑ Requires firmware support.
  5. ↑ No SSE4. No SSSE3.
  6. ↑ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  7. ↑ Unified shaders  : texture mapping units  : render output units
  8. 1 2 To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
  9. ↑ To feed more than two displays, the additional panels must have native DisplayPort support. [9] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
  10. 1 2 DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

See also

  1. ↑ "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020.
  2. ↑ "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
  3. ↑ "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
  4. 1 2 "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
  5. ↑ Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
  6. ↑ Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
  7. ↑ Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016
  8. ↑ "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.
  9. ↑ "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 8 December 2014.
  10. ↑ Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33" . Retrieved 16 January 2016.
  11. ↑ "Radeon feature matrix". freedesktop.org . Retrieved 10 January 2016.
  12. ↑ Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.
  13. 1 2 Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.

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