AMD Accelerated Processing Unit

Not to be confused with auxiliary power unit.

AMD Accelerated Processing Unit

Release date	2011 (Original); 2017 (Zen based)
Codename	Fusion Desna Ontario Zacate Llano Hondo Trinity Weatherford Richland Kaveri Godavari Kabini Temash Carrizo Bristol Ridge Raven Ridge Picasso Renoir Cezanne IGP Wrestler WinterPark BeaverCreek
Architecture	AMD64
Models	Desktop E2 Series Desktop A4/A6/A8/A10/A12 Series Notebook A, E and C Series AMD Athlon with Radeon Graphics AMD Ryzen with Radeon Graphics
Cores	1 to 8
Transistors	32 nm 1.178B (Llano) 32 nm 1.303B (Trinity) 32 nm 1.3B (Richland) 28 nm 2.41B (Kaveri) 14 nm 4.95B (Raven Ridge) 12 nm (Picasso) 7 nm (Renoir & Cezanne) 6 nm (Rembrandt)
API support
Direct3D	Direct3D 11 Direct3D 12
OpenCL	1.2
OpenGL	4.1+

AMD Accelerated Processing Unit (APU), formerly known as Fusion, is a series of 64-bit microprocessors from Advanced Micro Devices (AMD), combining a general-purpose AMD64 central processing unit (CPU) and 3D integrated graphics processing unit (IGPU) on a single die.

AMD announced the first generation APUs, Llano for high-performance and Brazos for low-power devices, in January 2011. The second generation Trinity for high-performance and Brazos-2 for low-power devices were announced in June 2012. The third generation Kaveri for high performance devices were launched in January 2014, while Kabini and Temash for low-power devices were announced in the summer of 2013. Since the launch of the Zen microarchitecture, Ryzen and Athlon APUs have released to the global market as Raven Ridge on the DDR4 platform, after Bristol Ridge a year prior.

AMD has also supplied semi-custom APUs for consoles starting with the release of Sony PlayStation 4 and Microsoft Xbox One eighth generation video game consoles.

History

The AMD Fusion project started in 2006 with the aim of developing a system on a chip that combined a CPU with a GPU on a single die. This effort was moved forward by AMD's acquisition of graphics chipset manufacturer ATI ^[1] in 2006. The project reportedly required three internal iterations of the Fusion concept to create a product deemed worthy of release. ^[1] Reasons contributing to the delay of the project include the technical difficulties of combining a CPU and GPU on the same die at a 45 nm process, and conflicting views on what the role of the CPU and GPU should be within the project. ^[2]

The first generation desktop and laptop APU, codenamed Llano, was announced on 4 January 2011 at the 2011 CES show in Las Vegas and released shortly thereafter. ^{[3] [4]} It featured K10 CPU cores and a Radeon HD 6000 series GPU on the same die on the FM1 socket. An APU for low-power devices was announced as the Brazos platform, based on the Bobcat microarchitecture and a Radeon HD 6000 series GPU on the same die. ^[5]

At a conference in January 2012, corporate fellow Phil Rogers announced that AMD would re-brand the Fusion platform as the Heterogeneous System Architecture (HSA), stating that "it's only fitting that the name of this evolving architecture and platform be representative of the entire, technical community that is leading the way in this very important area of technology and programming development." ^[6] However, it was later revealed that AMD had been the subject of a trademark infringement lawsuit by the Swiss company Arctic, who used the name "Fusion" for a line of power supply products. ^[7]

The second generation desktop and laptop APU, codenamed Trinity was announced at AMD's 2010 Financial Analyst Day ^{[8] [9]} and released in October 2012. ^[10] It featured Piledriver CPU cores and Radeon HD 7000 series GPU cores on the FM2 socket. ^[11] AMD released a new APU based on the Piledriver microarchitecture on 12 March 2013 for Laptops/Mobile and on 4 June 2013 for desktops under the codename Richland. ^[12] The second generation APU for low-power devices, Brazos 2.0, used exactly the same APU chip, but ran at higher clock speed and rebranded the GPU as Radeon HD 7000 series and used a new I/O controller chip.

Semi-custom chips were introduced in the Microsoft Xbox One and Sony PlayStation 4 video game consoles, ^{[13] [14]} and subsequently in the Microsoft Xbox Series X|S and Sony PlayStation 5 consoles.

A third generation of the technology was released on 14 January 2014, featuring greater integration between CPU and GPU. The desktop and laptop variant is codenamed Kaveri, based on the Steamroller architecture, while the low-power variants, codenamed Kabini and Temash, are based on the Jaguar architecture. ^[15]

Since the introduction of Zen-based processors, AMD renamed their APUs as the Ryzen with Radeon Graphics and Athlon with Radeon Graphics, with desktop units assigned with G suffix on their model numbers (e.g. Ryzen 5 3400G & Athlon 3000G) to distinguish them from regular processors or with basic graphics and also to differentiate away from their former Bulldozer era A-series APUs. The mobile counterparts were always paired with Radeon Graphics regardless of suffixes.

In November 2017, HP released the Envy x360, featuring the Ryzen 5 2500U APU, the first 4th generation APU, based on the Zen CPU architecture and the Vega graphics architecture. ^[16]

Features

Heterogeneous System Architecture

Main article: Heterogeneous System Architecture

AMD is a founding member of the Heterogeneous System Architecture (HSA) Foundation and is consequently actively working on developing HSA in cooperation with other members. The following hardware and software implementations are available in AMD's APU-branded products:

Type	HSA feature	First implemented	Notes
Optimized Platform	GPU Compute C++ Support	2012 Trinity APUs	Support OpenCL C++ directions and Microsoft's C++ AMP language extension. This eases programming of both CPU and GPU working together to process support parallel workloads.
	HSA-aware MMU		GPU can access the entire system memory through the translation services and page fault management of the HSA MMU.
	Shared Power Management		CPU and GPU now share the power budget. Priority goes to the processor most suited to the current tasks.
Architectural Integration	Heterogeneous Memory Management: the CPU's MMU and the GPU's IOMMU share the same address space. [17] [18]	2014 PlayStation 4, Kaveri APUs	CPU and GPU now access the memory with the same address space. Pointers can now be freely passed between CPU and GPU, hence enabling zero-copy .
	Fully coherent memory between CPU and GPU		GPU can now access and cache data from coherent memory regions in the system memory, and also reference the data from CPU's cache. Cache coherency is maintained.
	GPU uses pageable system memory via CPU pointers		GPU can take advantage of the shared virtual memory between CPU and GPU, and pageable system memory can now be referenced directly by the GPU, instead of being copied or pinned before accessing.
System Integration	GPU compute context switch	2015 Carrizo APU	Compute tasks on GPU can be context switched, allowing a multi-tasking environment and also faster interpretation between applications, compute and graphics.
	GPU graphics pre-emption		Long-running graphics tasks can be pre-empted so processes have low latency access to the GPU.
	Quality of service [17]		In addition to context switch and pre-emption, hardware resources can be either equalized or prioritized among multiple users and applications.

Feature overview

The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD Processors with 3D Graphics).

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Platform			High, standard and low power													Low and ultra-low power
Codename	Server	Basic						Toronto
		Micro															Kyoto
	Desktop	Performance													Raphael
		Mainstream	Llano	Trinity	Richland	Kaveri	Kaveri Refresh (Godavari)	Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir	Cezanne
		Entry
		Basic															Kabini				Dalí
	Mobile	Performance										Renoir	Cezanne	Rembrandt	Dragon Range
		Mainstream	Llano	Trinity	Richland	Kaveri		Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir Lucienne	Cezanne Barceló
		Entry																			Dalí			Mendocino
		Basic														Desna, Ontario, Zacate	Kabini, Temash	Beema, Mullins	Carrizo-L	Stoney Ridge		Pollock
	Embedded			Trinity		Bald Eagle		Merlin Falcon, Brown Falcon		Great Horned Owl		Grey Hawk				Ontario, Zacate	Kabini	Steppe Eagle, Crowned Eagle, LX-Family		Prairie Falcon	Banded Kestrel		River Hawk
Released			Aug 2011	Oct 2012	Jun 2013	Jan 2014	2015	Jun 2015	Jun 2016	Oct 2017	Jan 2019	Mar 2020	Jan 2021	Jan 2022	Sep 2022	Jan 2011	May 2013	Apr 2014	May 2015	Feb 2016	Apr 2019	Jul 2020	Jun 2022	Nov 2022
CPU microarchitecture			K10	Piledriver		Steamroller		Excavator	"Excavator+" [19]	Zen	Zen+	Zen 2	Zen 3	Zen 3+	Zen 4	Bobcat	Jaguar	Puma	Puma+ [20]	"Excavator+"	Zen		Zen+	"Zen 2+"
ISA			x86-64 v1	x86-64 v2						x86-64 v3					x86-64 v4	x86-64 v1	x86-64 v2				x86-64 v3
Socket	Desktop	Performance	—												AM5	—
		Mainstream	—					AM4						—
		Entry	FM1	FM2		FM2+		FM2+ [lower-alpha 1] , AM4	AM4					—
		Basic	—													—	AM1	—			FP5	—
	Other		FS1	FS1+, FP2		FP3		FP4		FP5		FP6		FP7	?	FT1	FT3	FT3b		FP4	FP5	FT5	FP5	FT6
PCI Express version			2.0			3.0								4.0	5.0	2.0				3.0
CXL			—													—
Fab. (nm)			GF 32SHP (HKMG SOI)			GF 28SHP (HKMG bulk)				GF 14LPP (FinFET bulk)	GF 12LP (FinFET bulk)	TSMC N7 (FinFET bulk)		TSMC N6 (FinFET bulk)	CCD: TSMC N5 (FinFET bulk) cIOD: TSMC N6 (FinFET bulk)	TSMC N40 (bulk)	TSMC N28 (HKMG bulk)	GF 28SHP (HKMG bulk)			GF 14LPP (FinFET bulk)		GF 12LP (FinFET bulk)	TSMC N6 (FinFET bulk)
Die area (mm2)			228	246		245		245	250	210 [21]		156	180	210		75 (+ 28 FCH)	107		?	125	149
Min TDP (W)			35	17				12				10		15	105	4.5	4	3.95	10	6			12	8
Max APU TDP (W)			100			95		65						45	170	18	25					6	54	15
Max stock APU base clock (GHz)			3	3.8	4.1	4.1		3.7	3.8	3.6	3.7	3.8	4.0	3.3	4.7	1.75	2.2	2	2.2	3.2	2.6	1.2	3.35	2.8
Max APUs per node [lower-alpha 2]			1													1
Max core dies per CPU			1												2	1
Max CCX per core die			1									2	1			1
Max cores per CCX			4										8			2	4			2			4
Max CPU [lower-alpha 3] cores per APU			4									8			16	2	4			2			4
Max threads per CPU core			1							2						1					2
Integer pipeline structure			3+3	2+2						4+2		4+2+1	1+3+3+1+2			1+1+1+1				2+2	4+2			4+2+1
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF
IOMMU [lower-alpha 4]			—	v2												v1		v2
BMI1, AES-NI, CLMUL, and F16C																—
MOVBE			—
AVIC, BMI2, RDRAND, and MWAITX/MONITORX																—
SME [lower-alpha 5] , TSME [lower-alpha 5] , ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing			—													—
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT			—													—
MPK, VAES			—													—
SGX			—													—
FPUs per core			1	0.5						1						1				0.5	1
Pipes per FPU			2													2
FPU pipe width			128-bit									256-bit				80-bit	128-bit							256-bit
CPU instruction set SIMD level			SSE4a [lower-alpha 6]	AVX				AVX2							AVX-512	SSSE3	AVX			AVX2
3DNow!			3DNow!+	—												—
PREFETCH/PREFETCHW
GFNI			—													—
AMX			—
FMA4, LWP, TBM, and XOP			—							—						—					—
FMA3
L1 data cache per core (KiB)			64	16				32								32
L1 data cache associativity (ways)			2	4				8								8
L1 instruction caches per core			1	0.5						1						1				0.5	1
Max APU total L1 instruction cache (KiB)			256	128		192				256					512	64		128		96	128
L1 instruction cache associativity (ways)			2			3				4		8				2				3	4			8
L2 caches per core			1	0.5						1						1				0.5	1
Max APU total L2 cache (MiB)			4					2				4			16	1	2			1			2
L2 cache associativity (ways)			16							8						16					8
Max on--die L3 cache per CCX (MiB)			—							4			16		32	—						4
Max 3D V-Cache per CCD (MiB)										—					64							—
Max total in-CCD L3 cache per APU (MiB)										4		8	16		64							4
Max. total 3D V-Cache per APU (MiB)										—					64							—
Max. board L3 cache per APU (MiB)										—												—
Max total L3 cache per APU (MiB)										4		8	16		128							4
APU L3 cache associativity (ways)										16												16
L3 cache scheme										Victim												Victim
Max. L4 cache			—													—
Max stock DRAM support			DDR3-1866		DDR3-2133			DDR3-2133, DDR4-2400	DDR4-2400	DDR4-2933		DDR4-3200, LPDDR4-4266		DDR5-4800, LPDDR5-6400	DDR5-5200	DDR3L-1333	DDR3L-1600	DDR3L-1866		DDR3-1866, DDR4-2400	DDR4-2400	DDR4-1600	DDR4-3200	LPDDR5-5500
Max DRAM channels per APU			2													1					2	1	2
Max stock DRAM bandwidth (GB/s) per APU			29.866		34.132			38.400		46.932		68.256		102.400	83200	10.666	12.800	14.933		19.200	38.400	12.800	51.200	88.000
GPU microarchitecture			TeraScale 2 (VLIW5)	TeraScale 3 (VLIW4)		GCN 2nd gen		GCN 3rd gen		GCN 5th gen [22]				RDNA 2nd gen		TeraScale 2 (VLIW5)	GCN 2nd gen			GCN 3rd gen [22]	GCN 5th gen			RDNA 2nd gen
GPU instruction set			TeraScale instruction set			GCN instruction set								RDNA instruction set		TeraScale instruction set	GCN instruction set							RDNA instruction set
Max stock GPU base clock (MHz)			600	800	844	866		1108		1250	1400	2100		2400	400	538	600	?	847	900	1200	600	1300	1900
Max stock GPU base GFLOPS [lower-alpha 7]			480	614.4	648.1	886.7		1134.5		1760	1971.2	2150.4		3686.4	102.4	86	?	?	?	345.6	460.8	230.4	1331.2	486.4
3D engine [lower-alpha 8]			Up to 400:20:8	Up to 384:24:6		Up to 512:32:8				Up to 704:44:16 [23]		Up to 512:32:8		768:48:8	128:?:?	80:8:4	128:8:4			Up to 192:12:8	Up to 192:12:4	192:12:4	Up to 512:?:?	128:?:?
			IOMMUv1			IOMMUv2										IOMMUv1		?		IOMMUv2
Video decoder			UVD 3.0			UVD 4.2		UVD 6.0		VCN 1.0 [24]		VCN 2.1 [25]	VCN 2.2 [25]	VCN 3.1		UVD 3.0	UVD 4.0	UVD 4.2	UVD 6.0	UVD 6.3	VCN 1.0			VCN 3.1
Video encoder			—	VCE 1.0		VCE 2.0		VCE 3.1								—	VCE 2.0		VCE 3.1
AMD Fluid Motion
GPU power saving			PowerPlay	PowerTune												PowerPlay	PowerTune [26]
TrueAudio			—			[27]							?			—
FreeSync						1 2											1 2
HDCP [lower-alpha 9]			?			1.4				1.4 2.2						?	1.4				1.4 2.2
PlayReady [lower-alpha 9]			—							3.0 not yet						—					3.0 not yet
Supported displays [lower-alpha 10]			2–3	2–4				3		3 (desktop) 4 (mobile, embedded)		4				2				3	4		4
/drm/radeon [lower-alpha 11] [29] [30]									—											—
/drm/amdgpu [lower-alpha 11] [31]			—			[32]										—	[32]

1. For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
2. A PC would be one node.
3. An APU combines a CPU and a GPU. Both have cores.
4. Requires firmware support.
5. Requires firmware support.
6. No SSE4. No SSSE3.
7. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
8. Unified shaders  : texture mapping units  : render output units
9. To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
10. To feed more than two displays, the additional panels must have native DisplayPort support. ^[28] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
11. DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

APU or Radeon Graphics branded platforms

For a more comprehensive list, see List of AMD Accelerated Processing Unit microprocessors.

AMD APUs have a unique architecture: they have AMD CPU modules, cache, and a discrete-class graphics processor, all on the same die using the same bus. This architecture allows for the use of graphics accelerators, such as OpenCL, with the integrated graphics processor. ^[33] The goal is to create a "fully integrated" APU, which, according to AMD, will eventually feature 'heterogeneous cores' capable of processing both CPU and GPU work automatically, depending on the workload requirement. ^[34]

TeraScale-based GPU

K10 architecture (2011): Llano

AMD A6-3650 (Llano)

Main article: AMD 10h

• "Stars" AMD K10-cores ^[35]
• Integrated Evergreen/VLIW5-based GPU (branded Radeon HD 6000 Series)
• Northbridge ^{[17] [18]}
• PCIe ^{[17] [18]}
• DDR3 ^{[17] [18]} memory controller to arbitrate between coherent and non-coherent memory requests. ^[36] The physical memory is partitioned between the GPU (up to 512  MB) and the CPU (the remainder). ^[36]
• Unified Video Decoder ^{[17] [18]}
• AMD Eyefinity multi-monitor-support

The first generation APU, released in June 2011, was used in both desktops and laptops. It was based on the K10 architecture and built on a 32 nm process featuring two to four CPU cores on a thermal design power (TDP) of 65-100 W, and integrated graphics based on the Radeon HD6000 Series with support for DirectX 11, OpenGL 4.2 and OpenCL 1.2. In performance comparisons against the similarly priced Intel Core i3-2105, the Llano APU was criticised for its poor CPU performance ^[37] and praised for its better GPU performance. ^{[38] [39]} AMD was later criticised for abandoning Socket FM1 after one generation. ^[40]

Bobcat architecture (2011): Ontario, Zacate, Desna, Hondo

Main article: Bobcat (microarchitecture)

• Bobcat-based CPU
• Evergreen/VLIW5-based GPU (branded Radeon HD 6000 Series and Radeon HD 7000 Series)
• Northbridge ^{[17] [18]}
• PCIe ^{[17] [18]} support.
• DDR3 SDRAM ^{[17] [18]} memory controller to arbitrate between coherent and non-coherent memory requests. ^[36] The physical memory is partitioned between the GPU (up to 512 MB) and the CPU (the remainder). ^[36]
• Unified Video Decoder (UVD) ^{[17] [18]}

The AMD Brazos platform was introduced on 4 January 2011, targeting the subnotebook, netbook and low power small form factor markets. ^[3] It features the 9-watt AMD C-Series APU (codename: Ontario) for netbooks and low power devices as well as the 18-watt AMD E-Series APU (codename: Zacate) for mainstream and value notebooks, all-in-ones and small form factor desktops. Both APUs feature one or two Bobcat x86 cores and a Radeon Evergreen Series GPU with full DirectX11, DirectCompute and OpenCL support including UVD3 video acceleration for HD video including 1080p. ^[3]

AMD expanded the Brazos platform on 5 June 2011 with the announcement of the 5.9-watt AMD Z-Series APU (codename: Desna) designed for the Tablet market. ^[41] The Desna APU is based on the 9-watt Ontario APU. Energy savings were achieved by lowering the CPU, GPU and northbridge voltages, reducing the idle clocks of the CPU and GPU as well as introducing a hardware thermal control mode. ^[41] A bidirectional turbo core mode was also introduced.

AMD announced the Brazos-T platform on 9 October 2012. It comprised the 4.5-watt AMD Z-Series APU (codenamed Hondo) and the A55T Fusion Controller Hub (FCH), designed for the tablet computer market. ^{[42] [43]} The Hondo APU is a redesign of the Desna APU. AMD lowered energy use by optimizing the APU and FCH for tablet computers. ^{[44] [45]}

The Deccan platform including Krishna and Wichita APUs were cancelled in 2011. AMD had originally planned to release them in the second half 2012. ^[46]

Piledriver architecture (2012): Trinity and Richland

Piledriver-based AMD APUs

An AMD A4-5300 for desktop systems

An AMD A10-4600M for mobile systems

Main article: Piledriver (microarchitecture)

• Piledriver-based CPU
• Northern Islands/VLIW4-based GPU (branded Radeon HD 7000 and 8000 Series)
• Unified Northbridge – includes AMD Turbo Core 3.0, which enables automatic bidirectional power management between CPU modules and GPU. Power to the CPU and GPU is controlled automatically by changing the clock rate depending on the load. For example, for a non-overclocked A10-5800K APU the CPU frequency can change from 1.4 GHz to 4.2 GHz, and the GPU frequency can change from 304 MHz to 800 MHz. In addition, CC6 mode is capable of powering down individual CPU cores, while PC6 mode is able to lower the power on the entire rail. ^[47]
• AMD HD Media Accelerator ^[48] – includes AMD Perfect Picture HD, AMD Quick Stream technology, and AMD Steady Video technology.
• Display controllers: AMD Eyefinity-support for multi-monitor set-ups, HDMI, DisplayPort 1.2, DVI

Trinity

The first iteration of the second generation platform, released in October 2012, brought improvements to CPU and GPU performance to both desktops and laptops. The platform features 2 to 4 Piledriver CPU cores built on a 32 nm process with a TDP between 65 W and 100 W, and a GPU based on the Radeon HD7000 Series with support for DirectX 11, OpenGL 4.2, and OpenCL 1.2. The Trinity APU was praised for the improvements to CPU performance compared to the Llano APU. ^[49]

Richland

• "Enhanced Piledriver" CPU cores ^[50]
• Temperature Smart Turbo Core technology. An advancement of the existing Turbo Core technology, which allows internal software to adjust the CPU and GPU clock speed to maximise performance within the constraints of the Thermal design power of the APU. ^[51]
• New low-power consumption CPUs with only 45 W TDP ^[52]

The release of this second iteration of this generation was 12 March 2013 for mobile parts and 5 June 2013 for desktop parts.

Graphics Core Next-based GPU

Jaguar architecture (2013): Kabini and Temash

Main article: Jaguar (microarchitecture)

• Jaguar-based CPU
• Graphics Core Next 2nd Gen-based GPU
• Socket AM1 and Socket FT3 support
• Target segment desktop and mobile

In January 2013 the Jaguar-based Kabini and Temash APUs were unveiled as the successors of the Bobcat-based Ontario, Zacate and Hondo APUs. ^{[53] [54] [55]} The Kabini APU is aimed at the low-power, subnotebook, netbook, ultra-thin and small form factor markets, while the Temash APU is aimed at the tablet, ultra-low power and small form factor markets. ^[55] The two to four Jaguar cores of the Kabini and Temash APUs feature numerous architectural improvements regarding power requirement and performance, such as support for newer x86-instructions, a higher IPC count, a CC6 power state mode and clock gating. ^{[56] [57] [58]} Kabini and Temash are AMD's first, and also the first ever quad-core x86 based SoCs. ^[59] The integrated Fusion Controller Hubs (FCH) for Kabini and Temash are codenamed "Yangtze" and "Salton", respectively. ^[60] The Yangtze FCH features support for two USB 3.0 ports, two SATA 6 Gbit/s ports, as well as the xHCI 1.0 and SD/SDIO 3.0 protocols for SD-card support. ^[60] Both chips feature DirectX 11.1-compliant GCN-based graphics as well as numerous HSA improvements. ^{[53] [54]} They were fabricated at a 28 nm process in an FT3 ball grid array package by Taiwan Semiconductor Manufacturing Company (TSMC), and were released on 23 May 2013. ^{[56] [61] [62]}

The PlayStation 4 and Xbox One were revealed to both be powered by 8-core semi-custom Jaguar-derived APUs.

Steamroller architecture (2014): Kaveri

AMD A8-7650K (Kaveri)

Main article: Steamroller (microarchitecture)

• Steamroller-based CPU with 2–4 cores ^[63]
• Graphics Core Next 2nd Gen-based GPU with 192–512 shader processors ^[64]
• 15–95 W thermal design power ^{[63] [64]}
• Fastest mobile processor of this series: AMD FX-7600P (35 W)
• Fastest desktop processor of this series: AMD A10-7850K (95 W)
• Socket FM2+ and Socket FP3 ^[63]
• Target segment desktop and mobile
• Heterogeneous System Architecture-enabled zero-copying through pointer passing

The third generation of the platform, codenamed Kaveri, was partly released on 14 January 2014. ^[65] Kaveri contains up to four Steamroller CPU cores clocked to 3.9 GHz with a turbo mode of 4.1 GHz, up to a 512-core Graphics Core Next GPU, two decode units per module instead of one (which allows each core to decode four instructions per cycle instead of two), AMD TrueAudio, ^[66] Mantle API, ^[67] an on-chip ARM Cortex-A5 MPCore, ^[68] and will release with a new socket, FM2+. ^[69] Ian Cutress and Rahul Garg of Anandtech asserted that Kaveri represented the unified system-on-a-chip realization of AMD's acquisition of ATI. The performance of the 45 W A8-7600 Kaveri APU was found to be similar to that of the 100 W Richland part, leading to the claim that AMD made significant improvements in on-die graphics performance per watt; ^[63] however, CPU performance was found to lag behind similarly specified Intel processors, a lag that was unlikely to be resolved in the Bulldozer family APUs. ^[63] The A8-7600 component was delayed from a Q1 launch to an H1 launch because the Steamroller architecture components allegedly did not scale well at higher clock speeds. ^[70]

AMD announced the release of the Kaveri APU for the mobile market on 4 June 2014 at Computex 2014, ^[64] shortly after the accidental announcement on the AMD website on 26 May 2014. ^[71] The announcement included components targeted at the standard voltage, low-voltage, and ultra-low voltage segments of the market. In early-access performance testing of a Kaveri prototype laptop, AnandTech found that the 35 W FX-7600P was competitive with the similarly priced 17 W Intel i7-4500U in synthetic CPU-focused benchmarks, and was significantly better than previous integrated GPU systems on GPU-focused benchmarks. ^[72] Tom's Hardware reported the performance of the Kaveri FX-7600P against the 35 W Intel i7-4702MQ, finding that the i7-4702MQ was significantly better than the FX-7600P in synthetic CPU-focused benchmarks, whereas the FX-7600P was significantly better than the i7-4702MQ's Intel HD 4600 iGPU in the four games that could be tested in the time available to the team. ^[64]

Puma architecture (2014): Beema and Mullins

Main article: Puma (microarchitecture)

• Puma-based CPU
• Graphics Core Next 2nd Gen-based GPU with 128 shader processors
• Socket FT3
• Target segment ultra-mobile

Puma+ architecture (2015): Carrizo-L

Main article: Puma (microarchitecture) § Puma+

• Puma+-based CPU with 2–4 cores ^[73]
• Graphics Core Next 2nd Gen-based GPU with 128 shader processors ^[73]
• 12–25 W configurable TDP ^[73]
• Socket FP4 support; pin-compatible with Carrizo ^[73]
• Target segment mobile and ultra-mobile

Excavator architecture (2015): Carrizo

Main article: Excavator (microarchitecture)

• Excavator-based CPU with 4 cores ^[74]
• Graphics Core Next 3rd Gen-based GPU
• Memory controller supports DDR3 SDRAM at 2133 MHz and DDR4 SDRAM at 1866 MHz ^[74]
• 15–35 W configurable TDP (with the 15 W cTDP unit having reduced performance) ^[74]
• Integrated southbridge ^[74]
• Socket FP4
• Target segment mobile
• Announced by AMD on YouTube (19 November 2014) ^[75]

Steamroller architecture (Q2–Q3 2015): Godavari

Main article: Steamroller (microarchitecture)

• Update of the desktop Kaveri series with higher clock frequencies or smaller power envelope
• Steamroller-based CPU with 4 cores ^[76]
• Graphics Core Next 2nd Gen-based GPU
• Memory controller supports DDR3 SDRAM at 2133 MHz
• 65/95 W TDP with support for configurable TDP
• Socket FM2+
• Target segment desktop
• Listed since Q2 2015

Excavator architecture (2016): Bristol Ridge and Stoney Ridge

AMD A12-9800 (Bristol Ridge)

Main article: Excavator (microarchitecture)

• Excavator-based CPU with 2–4 cores
• 1 MB L2 cache per module
• Graphics Core Next 3rd Gen-based GPU ^{[77] [78] [79] [80]}
• Memory controller supports DDR4 SDRAM
• 15/35/45/65 W TDP with support for configurable TDP
• 28 nm
• Socket AM4 for desktop
• Target segment desktop, mobile and ultra-mobile

Zen architecture (2017): Raven Ridge

Main articles: Zen (microarchitecture) and Ryzen § APUs: Raven Ridge

• Zen-based CPU cores ^[81] with simultaneous multithreading (SMT)
• 512 KB L2 cache per core
• 4 MB L3 cache
• Precision Boost 2 ^[82]
• Graphics Core Next 5th Gen "Vega"-based GPU ^[83]
• Memory controller supports DDR4 SDRAM
• Video Core Next as successor of UVD+VCE
• 14 nm at GlobalFoundries
• Socket FP5 for mobile ^[84] and AM4 for desktop
• Target segment desktop and mobile
• Listed since Q4 2017

Zen+ architecture (2019): Picasso

Main articles: Zen+ and Ryzen § APUs: Picasso

• Zen+-based CPU microarchitecture ^[85]
• Refresh of Raven Ridge on 12 nm with improved latency and efficiency/clock frequency. Features similar to Raven Ridge
• Launched January 2019

Zen 2 architecture (2020): Renoir

Main articles: Zen 2 and Renoir APUs

• Zen 2-based CPU microarchitecture ^[84]
• Graphics Core Next 5th Gen "Vega"-based GPU ^[86]
• VCN 2.1 ^[86]
• Memory controller supports DDR4 and LPDDR4X SDRAM up to 4266 MHz ^[86]
• 15 and 45 W TDP for mobile and 35 and 65 W TDP for desktop ^[84]
• 7 nm at TSMC ^[87]
• Socket FP6 for mobile and socket AM4 for desktop ^[84]
• Release early 2020 ^{[86] [87]}

Zen 3 architecture (2021): Cezanne

Main articles: Zen 3 and Cezanne APUs

• Zen 3-based CPU microarchitecture ^[88]
• Graphics Core Next 5th Gen "Vega"-based GPU ^[89]
• Memory controller supports DDR4 and LPDDR4X SDRAM up to 4266 MHz ^{[89] [88]}
• Up to 45 W TDP for mobile; ^[90] 35W to 65W TDP for desktop. ^[89]
• 7 nm at TSMC ^[88]
• Socket AM4 for desktop ^[89]
• Socket FP6 for mobile
• Released for mobiles early 2021 ^[88] with desktop counterparts released in April 2021. ^[89]

RDNA-based GPU

Zen 3+ architecture (2022): Rembrandt

• Zen 3+ based CPU microarchitecture ^[91]
• RDNA 2-based GPU ^[91]
• Memory controller supports DDR5-4800 and LPDDR5-6400 ^[91]
• Up to 45 W TDP for mobile
• Node: TSMC N6 ^[91]
• Socket FP7 for mobile
• Released for mobiles early 2022 ^[91]

See also

• List of AMD accelerated processing units
• Ryzen
• AMD mobile platform
• List of AMD mobile microprocessors
• Radeon
• Intel Graphics Technology
• List of Nvidia graphics processing units

References

1. "The rise and fall of AMD: A company on the ropes". 23 April 2013. Retrieved 20 December 2013.
2. William Van Winkle (13 August 2012). "AMD Fusion: How It Started, Where It's Going, And What It Means" . Retrieved 20 December 2013.
3. AMD (4 January 2011). "AMD Fusion APU Era Begins" . Retrieved 24 August 2013.
4. Stokes, Jon (8 February 2010). "AMD reveals Fusion CPU+GPU, to challenge Intel in laptops". Ars Technica. Archived from the original on 10 February 2010. Retrieved 9 February 2010.
5. Kowaliski, Cyril (9 November 2010). "A closer look at AMD's Brazos platform". The Tech Report. Retrieved 15 June 2017.
6. "AMD ditches Fusion branding". Bit-tech. Retrieved 24 July 2013.
7. "AMD targeted by Arctic over Fusion brand". Bit-tech. Retrieved 24 July 2013.
8. Cyril Kowaliski (9 November 2010). "AMD begins shipping Brazos, announces Bulldozer-based APUs". The Tech Report. Retrieved 7 January 2014.
9. Rick Bergman (9 November 2010). "AMD 2010 Financial Analyst Day". Advanced Micro Devices, Inc. Archived from the original (PDF) on 18 January 2016. Retrieved 7 January 2014.
10. "AMD reveals its 2012-2013 roadmap, promises 28 nm chips across the board by 2013". Engadget. 2 February 2012. Archived from the original on 2 March 2019. Retrieved 22 August 2012.
11. Kingsley-Hughes, Adrian. "Building an AMD 'Trinity' desktop PC - ZDNet". ZDNet .
12. "AMD launches "Richland" A-Series APUs: slight speed bump, better power management 404". Archived from the original on 19 July 2013.
13. Taylor, John (21 February 2013). "AMD and The Sony PS4. Allow Me To Elaborate". Archived from the original on 26 May 2013. Retrieved 30 August 2013.
14. "XBox One Revealed". Wired. 21 May 2013. Retrieved 23 May 2013.
15. Darren Murph. "AMD announces Temash, Kabini, Richland, and Kaveri APUs at CES 2013 (video)" . Retrieved 20 December 2013.
16. Ridley, Jacob (15 November 2017). "AMD Raven Ridge - Ryzen Mobile release date, specs, and performance" . Retrieved 30 November 2017.
17. "The programmer's guide to the APU galaxy" (PDF).
18. Shimpi, Anand Lal. "AMD Outlines HSA Roadmap: Unified Memory for CPU/GPU in 2013, HSA GPUs in 2014". www.anandtech.com.
19. "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020.
20. "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
21. "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
22. "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
23. Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
24. Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
25. "AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. 12 August 2021. Retrieved 25 August 2021.
26. Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016
27. "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.
28. "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 8 December 2014.
29. Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33" . Retrieved 16 January 2016.
30. "Radeon feature matrix". freedesktop.org . Retrieved 10 January 2016.
31. Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.
32. Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.
33. APU101_Final_Jan 2011.pdf
34. Shimpi, Anand Lal. "AMD Outlines HSA Roadmap: Unified Memory for CPU/GPU in 2013, HSA GPUs in 2014". AnandTech.
35. "AMD Llano core". Cpu-world.com. 17 March 2014. Retrieved 24 March 2014.
36. Kanter, David. "AMD Fusion Architecture and Llano".
37. Anand Lal Shimpi (30 June 2011). "The AMD A8-3850 Review: Llano on the Desktop". Anandtech. Retrieved 12 January 2014.
38. "Conclusion - AMD A8-3850 Review: Llano Rocks Entry-Level Desktops". 30 June 2011.
39. Shimpi, Anand Lal. "The AMD A8-3850 Review: Llano on the Desktop". AnandTech.
40. Shimpi, Anand Lal. "AMD A10-5800K & A8-5600K Review: Trinity on the Desktop, Part 1". AnandTech.
41. Nita, Sorin (1 June 2011). "AMD Releases More Details Regarding the Desna Tablet APU" . Retrieved 20 March 2013.
42. AMD (9 October 2013). "New AMD Z-Series APU for Tablets Enables Immersive Experience for Upcoming Microsoft Windows 8 Platforms" . Retrieved 20 March 2013.
43. Shvets, Anthony (10 October 2012). "AMD announces Z-60 APU for tablets".
44. Hruska, Joel (9 October 2012). "AMD's Hondo Z-Series APU To Challenge Intel's Atom In Windows 8 Tablet Market". Archived from the original on 23 September 2020. Retrieved 20 March 2013.
45. Shilov, Anton (9 October 2012). "AMD Introduces Its First Accelerated Processing Unit for Media Tablets". Archived from the original on 9 February 2013. Retrieved 20 March 2013.
46. Demerjian, Charlie (15 November 2011). "Exclusive: AMD kills Wichita and Krishna". SemiAccurate. Retrieved 22 August 2012.
47. "CPU + GPU = APU: East Meets West". 14 June 2011. Retrieved 1 September 2013.
48. "AMD's 2nd Generation APU, Codenamed "Trinity," Will Enable Superior Multimedia Experience for Our "Connected" Generation". Archived from the original on 7 April 2013.
49. Shimpi, Anand Lal. "The AMD A8-3850 Review: Llano on the Desktop". AnandTech.
50. "AMD Officially Announces Third Generation Richland A-Series Mobile APUs - 50% Faster GPU Than Intel Core i7 Mobile". 12 March 2013.
51. "New Details Revealed on AMD's Upcoming Richland Chips". 12 March 2013.
52. "AMD A10-Series A10-6700T — AD670TYHA44HL / AD670TYHHLBOX". Cpu-world.com. Retrieved 10 November 2013.
53. SKYMTL (9 January 2013). "Richland, Kaveri, Kabini & Temash; AMD's 2013 APU Lineup Examined". Hardwarecanucks. Retrieved 23 March 2013.
54. Halfacree, Gareth (8 January 2013). "AMD unveils new APUs, SoCs and Radeon HD 8000 Series". Bit-Tech. Retrieved 23 March 2013.
55. Lal Shimpi, Anand (2 February 2012). "AMD's 2012 - 2013 Client CPU/GPU/APU Roadmap Revealed". AnandTech. Retrieved 8 August 2012.
56. Shilov, Anton (2 January 2013). "AMD to Officially Roll-Out "Kabini" and "Temash" Low-Power APUs This Quarter". X-bit labs. Archived from the original on 17 January 2013. Retrieved 21 March 2013.
57. Shilov, Anton (24 July 2013). "AMD's New Low-Power Micro-Architecture to Support AVX, BMI Other New Instructions". X-bit labs. Archived from the original on 9 February 2013. Retrieved 21 March 2013.
58. Paul, Donald (21 October 2012). "Leaked details of the future some Kabini APU AMD". Technewspedia. Archived from the original on 31 August 2014. Retrieved 21 March 2013.
59. Paine, Steve Chippy (9 January 2013). "AMD Shares SoC Line-Up for 2013. Kabini is for Ultrathins". Ultrabooknews. Retrieved 21 March 2013.
60. Abazovic, Fuad (24 January 2013). "Kabini chipset is Yangtze". Fudzilla. Retrieved 21 March 2013.
61. Hruska, Paul (14 January 2013). "AMD quietly confirms 28 nm Kabini, Temash chips are being built at TSMC". Extremetech. Retrieved 21 March 2013.
62. "AMDs sparsame Mobilprozessoren Kabini und Temash legen los". 23 May 2013. Retrieved 31 August 2013.
63. "AMD Kaveri Review: A8-7600 and A10-7850K Tested". Anandtech . Retrieved 20 May 2014.
64. "AMD FX-7600P Kaveri Review: FX Rides Again...In A Mobile APU?". Tom's Hardware. Retrieved 8 June 2014.
65. "AnandTech Portal | AMD Kaveri APU Launch Details: Desktop, January 14th". Anandtech.com. Retrieved 13 January 2014.
66. ChrisFiebelkorn on 3 Dec 2013 (2 December 2013). "AMD A10 Kaveri APU Details Leaked". HotHardware. Retrieved 13 January 2014.
67. Dave_HH on 14 Nov 2013 (13 November 2013). "How AMD's Mantle Will Redefine Gaming, AMD Hardware Not Required". HotHardware. Retrieved 13 January 2014.
68. "AMD and ARM Fusion redefine beyond x86". Archived from the original on 5 November 2013. Retrieved 20 July 2012.
69. "AMD's Next-Gen "Kaveri" APUs Will Require New Mainboards - X-bit labs".
70. "Perils of a paper launch: AMD's A8-7600 pushed back to late 2014". Extreme Tech . Retrieved 20 May 2014.
71. "AMD Publishes Mobile Kaveri Specifications". Anandtech . Retrieved 29 May 2014.
72. "AMD Launches Mobile Kaveri APUs". AnandTech . Retrieved 8 June 2014.
73. "AMD's Carrizo-L APUs Unveiled: 12-25W Quad Core Puma+". AnandTech . Retrieved 1 September 2015.
74. "AMD Details Carrizo APUs Energy Efficient Design at Hot Chips 2015 – 28nm Bulk High Density Design With 3.1 Billion Transistors, 250mm2 Die". WCCFTech. 26 August 2015. Retrieved 1 September 2015.
75. "Preview AMD's next gen APU (Carrizo)". YouTube .
76. "PC gaming hardware | PC Gamer".
77. Shilov, Anton. "AMD preps 'Bristol Ridge' APUs: 'Carrizo' for desktops". KitGuru. Retrieved 5 April 2016.
78. Cutress, Ian (5 April 2016). "AMD Pre-Announces Bristol Ridge in Notebooks: The 7th Generation APU". AnandTech.com. AnandTech.com. Retrieved 5 April 2016.
79. Kampman, Jeff (5 April 2016). "AMD lifts the curtain a little bit on its Bristol Ridge APUs". TechReport.com. Retrieved 5 April 2016.
80. Cutress, Ian (1 June 2016). "AMD Announces 7th Generation APU". Anandtech.com. Retrieved 1 June 2016.
81. Larabel, Michael (13 December 2016). "AMD Reveals More Zen CPU Details, Officially Known As Ryzen, No Linux Details Yet". Phoronix. Retrieved 13 December 2016.
82. Hallock, Robert (27 November 2017). "Understanding Precision Boost 2 in AMD SenseMI technology". AMD. Retrieved 19 December 2019.
83. Ferreira, Bruno (16 May 2017). "Ryzen Mobile APUs are coming to a laptop near you". Tech Report. Retrieved 16 May 2017.
84. Mujtaba, Hassan (18 December 2019). "AMD Ryzen 4000 APU Lineup For Desktop & Mobility Platforms Leaked". Wccftech. Retrieved 19 December 2019.
85. Cutress, Ian (6 January 2019). "AMD at CES 2019: Ryzen Mobile 3000-Series Launched, 2nd Gen Mobile at 15W and 35W, and Chromebooks". anandtech.com. AnandTech . Retrieved 12 November 2019.
86. btarunr (3 September 2019). "AMD "Renoir" APU to Support LPDDR4X Memory and New Display Engine". TechPowerUp. Retrieved 19 December 2019.
87. Pirzada, Usman (11 November 2019). "AMD Renoir APU Launching CES 2020, Will Destroy The NVIDIA MX 250 And Iris Pro Graphics". Wccftech. Retrieved 19 December 2019.
88. Anandtech. "AMD Launches Ryzen 5000 Mobile: Zen 3 and Cezanne for Notebooks". Anandtech. Retrieved 18 January 2021.
89. Anandtech. "AMD Ryzen 5000G APUs: OEM Only For Now, Full Release Later This Year". Anandtech. Retrieved 15 April 2021.
90. AMD. "AMD Ryzen Mobile Processors with Radeon Graphics". AMD. Retrieved 18 January 2021.
91. Anandtech. "AMD Announces Ryzen 6000 Mobile CPUs for Laptops: Zen3+ on 6nm with RDNA2 Graphics".

External links

• HSA Heterogeneous System Architecture Overview on YouTube by Vinod Tipparaju at SC13 in November 2013
• HSA and the software ecosystem
• HSA