Icarus Verilog

Last updated
Icarus Verilog
Developer(s) Stephen Williams
Stable release
12.0 / 10 June 2023;7 months ago (2023-06-10)
Repository
Written inC++
Operating system Linux, FreeBSD, OpenSolaris, AIX, Microsoft Windows, and Mac OS X
Platform Cross-platform
Available inEnglish
Type Verilog Simulator
License GPL-2.0-or-later
Website https://steveicarus.github.io/iverilog/

Icarus Verilog is an implementation of the Verilog hardware description language compiler that generates netlists in the desired format (EDIF) and a simulator. It supports the 1995, 2001 and 2005 versions of the standard, portions of SystemVerilog, and some extensions.

Contents

Icarus Verilog is available for Linux, FreeBSD, OpenSolaris, AIX, Microsoft Windows, and Mac OS X . Released under the GNU General Public License, Icarus Verilog is free software, an alternative to proprietary software like Cadence's Verilog-XL.

As of release 0.9, Icarus is composed of a Verilog compiler (including a Verilog preprocessor) with support for plug-in backends, and a virtual machine that simulates the design. To view waveforms, a program like GTKWave can be used. Release v10.0, besides general improvements and bug fixes, added preliminary support for VHDL, but the VHDL support has been abandoned as of 2018.

History

Not even the author quite remembers when the project was first started, but CVS records go back to 1998. There have been releases 0.2 through the current stable release 10.0.

Icarus Verilog development is done largely by the sole regular author, Stephen Williams. Some non-trivial portions have been contributed as accepted patches.

See also


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