555 timer IC

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555 timer IC
Signetics NE555N.JPG
Signetics NE555 in 8-pin DIP package
Type Active, integrated circuit
Invented Hans Camenzind (1971)
First production 1972
Electronic symbol
555 esquema.png
Internal block diagram [1]

The 555 timer IC is an integrated circuit used in a variety of timer, delay, pulse generation, and oscillator applications. It is one of the most popular timing ICs due to its flexibility and price. Derivatives provide two (556) or four (558) timing circuits in one package. [2] The design was first marketed in 1972 by Signetics [3] [4] and used bipolar junction transistors. Since then, numerous companies have made the original timers and later similar low-power CMOS timers. In 2017, it was said that over a billion 555 timers are produced annually by some estimates, and that the design was "probably the most popular integrated circuit ever made". [5]

Contents

History

Silicon die of the first 555 chip (1971) Die of the first 555 chip.jpg
Silicon die of the first 555 chip (1971)
Die of a CMOS NXP ICM7555 chip NXP-7555-HD.jpg
Die of a CMOS NXP ICM7555 chip

The timer IC was designed in 1971 by Hans Camenzind under contract to Signetics. [3] In 1968, he was hired by Signetics to develop a phase-locked loop (PLL) IC. He designed an oscillator for PLLs such that the frequency did not depend on the power supply voltage or temperature. Signetics subsequently laid off half of its employees due to the 1970 recession, and development on the PLL was thus frozen. [6] Camenzind proposed the development of a universal circuit based on the oscillator for PLLs and asked that he develop it alone, borrowing equipment from Signetics instead of having his pay cut in half. Camenzind's idea was originally rejected, since other engineers argued the product could be built from existing parts sold by the company; however, the marketing manager approved the idea. [7]

The first design for the 555 was reviewed in the summer of 1971. [8] After this design was tested and found to be without errors, Camenzind got the idea of using a direct resistance instead of a constant current source, finding that it worked satisfactorily. [8] The design change decreased the required 9 external pins to 8, so the IC could be fit in an 8-pin package instead of a 14-pin package. [8] This revised version passed a second design review, and the prototypes were completed in October 1971 as the NE555V (plastic DIP) and SE555T (metal TO-5). [9] The 9-pin version had already been released by another company founded by an engineer who had attended the first review and had retired from Signetics; that firm withdrew its version soon after the 555 was released. The 555 timer was manufactured by 12 companies in 1972, and it became a best-selling product. [6]

The 555 found many applications beyond timers. Camenzind noted in 1997 that "nine out of 10 of its applications were in areas and ways I had never contemplated. For months I was inundated by phone calls from engineers who had new ideas for using the device." [8]

Name

Several books report the name "555" timer IC derived from the three 5 kΩ resistors inside the chip. [10] [11] [12] However, in a recorded interview with an online transistor museum curator, [13] Hans Camenzind said "It was just arbitrarily chosen. It was Art Fury (marketing manager) who thought the circuit was gonna sell big who picked the name '555' timer IC.." [14]

Design

Depending on the manufacturer, the standard 555 package incorporated the equivalent of 25 transistors, 2 diodes, and 15 resistors on a silicon chip packaged into an 8-pin dual in-line package (DIP-8). [15] Variants available included the 556 (a DIP-14 combining two complete 555s on one chip), [16] and 558 / 559 (both variants were a DIP-16 combining four reduced-functionality timers on one chip). [2]

The NE555 parts were commercial temperature range, 0 °C to +70 °C, and the SE555 part number designated the military temperature range, −55 °C to +125 °C. These chips were available in both high-reliability metal can (T package) and inexpensive epoxy plastic (V package) form factors. Thus, the full part numbers were NE555V, NE555T, SE555V, and SE555T.

Low-power CMOS versions of the 555 are now available, such as the Intersil ICM7555 and Texas Instruments LMC555, TLC555, TLC551. [17] [18] [19] [20]

Internal schematic

The internal block diagram and schematic of the 555 timer are highlighted with the same color across all three drawings to clarify how the chip is implemented: [2]

Pinout

The pinout of the 8-pin 555 timer [1] and 14-pin 556 dual timer [21] are shown in the following table. Since the 556 is conceptually two 555 timers that share power pins, the pin numbers for each half are split across two columns. [2]

In the following table, longer pin designations are used, because manufacturers never standardized the abbreviated pin names across all datasheets.

555 pin#556 (unit 1)556 (unit 2)Pin namePin directionPin description [1] [21] [2]
1
7
GND
Power
Ground supply: this pin is the ground reference voltage (zero volts). [22]
2
6
8
TRIGGER
Input
Trigger: when VTRIGGER falls below 12VCONTROL (13VCC, except when CONTROL is driven by an external signal), OUTPUT goes to the high state and a timing interval starts. [22] As long as TRIGGER continues to be kept at a low voltage, OUTPUT will remain in the high state.
3
5
9
OUTPUT
Output
Output: this pin is a push-pull (P.P.) output that is driven to either a low state (GND) or a high state (VCC minus approximately 1.7 volts for bipolar timers, or VCC for CMOS timers). For bipolar timers, this pin can drive up to 200 mA, but CMOS timers are able to drive less (varies by chip). For bipolar timers, if this pin drives an edge-sensitive input of a digital logic chip, a 100 to 1000 pF decoupling capacitor (between this pin and GND) may need to be added to prevent double triggering. [2]
4
4
10
RESET
Input
Reset: a timing interval may be reset by driving this pin to GND, but the timing does not begin again until this pin rises above approximately 0.7 volts. This pin overrides TRIGGER, which in turn overrides THRESHOLD. If this pin is not used, it should be connected to VCC to prevent electrical noise accidentally causing a reset. [23] [22]
5
3
11
CONTROL
Input
Control: this pin provides access to the internal voltage divider (23VCC by default). By applying a voltage to this pin, the timing characteristics can be changed. In astable mode, this pin can be used to frequency-modulate the OUTPUT state. [16] If this pin is not used, it should be connected to a 10 nF decoupling capacitor (between this pin and GND) to ensure electrical noise doesn't affect the internal voltage divider. [2] [23] [22]
6
2
12
THRESHOLD
Input
Threshold: when the voltage at this pin is greater than VCONTROL (23VCC by default except when CONTROL is driven by an external signal), then the OUTPUT high state timing interval ends, causing OUTPUT to go to the low state. [22]
7
1
13
DISCHARGE
Output
Discharge: This pin is an open-collector (O.C.) output for bipolar timers, or an open-drain (O.D.) output for CMOS timers. This pin can be used to discharge a capacitor when OUTPUT is low. In bistable latch and bistable inverter modes, this pin is unused, which allows it to be used as an alternate output. [22]
8
14
VCC
Power
Positive supply: For bipolar timers, the supply voltage range is typically 4.5 to 16 volts (some are spec'ed for up to 18 volts, though most will operate as low as 3 volts). For CMOS timers, the supply voltage range is typically 2 to 15 volts (some are spec'ed for up to 18 volts, and some are spec'ed as low as 1 volt). See the supply min and max columns in the derivatives table in this article. Decoupling capacitor(s) are generally applied (between this pin and GND) as a good practice. [24] [23]

Modes

The 555 IC has the following operating modes:

  1. Astable (free-running) mode – The 555 operates as an electronic oscillator. Applications include:
  2. Monostable (one-shot) mode – The 555 operates as a "one-shot" pulse generator. Applications include:
    • timers, missing pulse detection, bounce-free switches, touch switches, frequency dividers, triggered measurement of resistance or capacitance, PWM, etc.
  3. Bistable (latch) mode – The 555 operates as a set-reset latch. Applications include:
  4. Schmitt trigger (inverter) mode – the 555 operates as a Schmitt trigger inverter gate. Application:
    • Converts a noisy input into a clean digital output.

Astable

Schematic of a 555 timer in astable mode 555 Astable Diagram.svg
Schematic of a 555 timer in astable mode
Waveform in astable mode NE555 Astable Waveforms.svg
Waveform in astable mode
Astable mode examples with common values
Frequency C R1 R2 Duty cycle
0.1 Hz (+0.048%)100 μF8.2 68 52.8%
1 Hz (+0.048%)10 μF8.2 68 52.8%
10 Hz (+0.048%)1 μF8.2 68 52.8%
100 Hz (+0.048%)100 nF8.2 68 52.8%
1 kHz (+0.048%)10 nF8.2 68 52.8%
10 kHz (+0.048%)1 nF8.2 68 52.8%
100 kHz (+0.048%)100 pF8.2 68 52.8%

In the astable configuration, the 555 timer puts out a continuous stream of rectangular pulses having a specific period.

The astable configuration is implemented using two resistors, and and one capacitor . The threshold and trigger pins are both connected to the capacitor; thus they have the same voltage.

Its repeated operating cycle (starting with the capacitor uncharged) is:

  1. Since the capacitor's voltage will be below 13 VCC, the trigger pin causes the 555's internal latch to change state, causing OUT to go high and the internal discharge transistor to cut-off.
  2. Since the discharge pin is no longer short-circuited to ground, the capacitor starts charging via current from Vcc through the resistors and .
  3. Once the capacitor charge reaches 23 Vcc, the threshold pin causes the 555's internal latch to change state, causing OUT to go low and the internal discharge transistor to go into saturation (maximal-conductivity) mode.
  4. This discharge transistor provides a discharge path, so the capacitor starts discharging through .
  5. Once the capacitor's voltage drops below 13 VCC, the cycle repeats from step 1.

During the first pulse, the capacitor charges from 0 V to 23 VCC, however, in later pulses, it only charges from 13 VCC to 23 VCC. Consequently, the first pulse has a longer high time interval compared to later pulses. Moreover, the capacitor charges through both resistors but only discharges through , thus the output high interval is longer than the low interval. This is shown in the following equations:

The output high time interval of each pulse is given by: [16]

The output low time interval of each pulse is given by: [16]

Hence, the frequency of the pulse is given by: [16]

and the duty cycle is given by: [16]

where is the time in seconds, is the resistance in ohms, is the capacitance in farads, and is the natural logarithm of 2. [lower-alpha 1]

Schematic of a 555 timer in astable mode with a 1N4148 diode to create a duty cycles less than 50% 555 Mk-sp Diagram.svg
Schematic of a 555 timer in astable mode with a 1N4148 diode to create a duty cycles less than 50%

Resistor requirements:

Shorter duty cycle

To create an output high time shorter than the low time (i.e., a duty cycle less than 50%) a fast diode (i.e. 1N4148 signal diode) can be placed in parallel with R2, with the cathode on the capacitor side. [16] This bypasses R2 during the high part of the cycle, so that the high interval depends only on R1 and C, with an adjustment based on the voltage drop across the diode. The low time is unaffected by the diode and so remains But the diode's forward voltage drop Vdiode slows charging on the capacitor, so the high time is longer than the often-cited to become:

where Vdiode is when the diode's "on" current is 12 of VCC/R1 (which depends on the type of diode and can be found in datasheets or measured). When Vdiode is small relative to Vcc, this charging is faster and approaches but is slower the closer Vdiode is to Vcc:

As an extreme example, when VCC = 5 V, and Vdiode = 0.7 V, high time is 1.00 R1C, which is 45% longer than the "expected" 0.693 R1C. At the other extreme, when Vcc = 15 V, and Vdiode = 0.3 V, the high time is 0.725 R1C, which is closer to the expected 0.693 R1C. The equation approaches 0.693 R1C as Vdiode approaches 0 V.

Voltage-controlled pulse-width modulation

In the previous example schematics, the control pin was not used, thus it should connected to ground through a 10  nF decoupling capacitor to shunt electrical noise. However if a time-varying voltage source was applied to the control pin, then the pulse widths would be dependent on the control voltage.

Monostable

Schematic of a 555 in monostable mode. Example values C = 100 nF, R = 180 kO to 220 kO for debouncing a pulled-up pushbutton. 555 Monostable.svg
Schematic of a 555 in monostable mode. Example values C = 100 nF, R = 180 kΩ to 220 kΩ for debouncing a pulled-up pushbutton.
Waveform in monostable mode NE555 Monotable Waveforms (English).png
Waveform in monostable mode

Monostable mode produces an output pulse when the trigger signals drops below 13VCC. An RC circuit sets the output pulse's duration as the time in seconds it takes to charge C to 23VCC: [16]

where is the resistance in ohms, is the capacitance in farads, is the natural log of 3 constant. [lower-alpha 2] The output pulse duration can be lengthened or shortened as desired by adjusting the values of R and C. Subsequent triggering before the end of this timing interval won't affect the output pulse. [25]

After the timing interval completes, the capacitor is almost instantly discharged through the Discharge pin, to then allow for subsequent triggering.

Example Values

Monostable mode examples with common values
Time C R
100 μs (−0.026%)1 nF91 kΩ
1 ms (−0.026%)10 nF91 kΩ
10 ms (−0.026%)100 nF91 kΩ
100 ms (−0.026%)1 μF91 kΩ
1 s (−0.026%)10 μF91 kΩ
10 s (−0.026%)100 μF91 kΩ

The table of common values (right) are solutions to that timing equation.

Scaling R and C by opposite powers of 10 will provide the same timing. For instance:

  • 1 ms ≅ 1 nF and 910 kΩ,
  • 1 ms ≅ 10 nF and 91 kΩ (values from table),
  • 1 ms ≅ 100 nF and 9.1 kΩ.

For each row in the example table (right), additional timing values can easily be created by adding one to three of the same resistor value in parallel and/or series. A second resistor in parallel, the new timing is half the table time. A second resistor in series, the new timing is double the table time.

  • 2.5 ms (0.25x) ≅ 100 nF and 22.75 kΩ (four 91 kΩ resistors in parallel),
  • 5 ms (0.5x) ≅ 100 nF and 45.5 kΩ (two 91 kΩ resistors in parallel),
  • 10 ms (1x) ≅ 100 nF and 91 kΩ (values from table),
  • 15 ms (1.5x) ≅ 100 nF and 136.5 kΩ (one 91 kΩ resistor in series with "two 91 kΩ resistors in parallel"),
  • 20 ms (2x) ≅ 100 nF and 182 kΩ (two 91 kΩ resistors in series),
  • 25 ms (2.5x) ≅ 100 nF and 227.5 kΩ ("two 91 kΩ resistors in series" in series with "two 91 kΩ resistors in parallel"),
  • 30 ms (3x) ≅ 100 nF and 273 kΩ (three 91 kΩ resistors in series),
  • 40 ms (4x) ≅ 100 nF and 364 kΩ (four 91 kΩ resistors in series).

Bistable SR latch

Schematic of a 555 in bistable SR latch mode. 555 Bistabiel digitaal.svg
Schematic of a 555 in bistable SR latch mode.
Active-low SR latch symbol, but lacks /Q output. Inverted SR Flip-flop.svg
Active-low SR latch symbol, but lacks /Q output.

A 555 timer can act as an active-low SR latch (though without an inverted Q output) with two outputs: output pin is a push-pull output, discharge pin is an open-collector output (requires a pull-up resistor).

For the schematic on the right, a Reset input signal connects to the RESET pin and connecting a Set input signal to the TR pin. Thus, pulling Set momentarily low acts as a "set" and transitions the output to the high state (VCC). Conversely, pulling Reset momentarily low acts as a "reset" and transitions the Out pin to the low state (GND).

No timing capacitors are required in a bistable configuration. The threshold input is grounded because it is unused. [26] The trigger and reset inputs may be held high via pull-up resistors if they are normally Hi-Z and only enabled by connecting to ground.

Bistable schmitt trigger inverter gate

Schematic of a 555 timer in bistable Schmitt trigger inverter mode. Example values C = 100 nF, R1 & R2 = 100 kO. 555 Bistabiel analoog.svg
Schematic of a 555 timer in bistable Schmitt trigger inverter mode. Example values C = 100 nF, R1 & R2 = 100 kΩ.
Schmitt trigger inverter symbol. Inverting Schmitt trigger symbol.svg
Schmitt trigger inverter symbol.

A 555 timer can be used to create a Schmitt trigger inverter gate with two outputs: output pin is a push-pull output, discharge pin is an open-collector output (requires a pull-up resistor).

For the schematic on the right, an input signal is AC-coupled through a low value series capacitor, then biased by identical high-resistance resistors and , which causes the signal to be centered at 12Vcc. This centered signal is connected to both the trigger and threshold input pins of the timer. The input signal must be strong enough to excite the trigger levels of the comparators to exceed the lower 13VCC and upper 23VCC thresholds in order to cause them to change state, thus providing the schmitt trigger feature. [27]

No timing capacitors are required in a bistable configuration.

Packages

Texas Instruments NE555 in DIP-8 and SO-8 packages NE555 DIP & SOIC.jpg
Texas Instruments NE555 in DIP-8 and SO-8 packages

In 1972, Signetics originally released the 555 timer in DIP-8 and TO5-8 metal can packages, and the 556 timer was released in a DIP-14 package. [4]

In 2006, the dual 556 timer was available in through-hole packages as DIP-14 (2.54 mm pitch), [21] and surface-mount packages as SO-14 (1.27 mm pitch) and SSOP-14 (0.65 mm pitch).

In 2012, the 555 was available in through-hole packages as DIP-8 (2.54 mm pitch), [28] and surface-mount packages as SO-8 (1.27 mm pitch), SSOP-8 / TSSOP-8 / VSSOP-8 (0.65 mm pitch), BGA (0.5 mm pitch). [1]

The MIC1555 is a CMOS 555-type timer with three fewer pins available in SOT23-5 (0.95 mm pitch) surface-mount package. [29]

Specifications

555 timer circuit in a solderless breadboard BjornR breadboard 01.jpg
555 timer circuit in a solderless breadboard

These specifications apply to the original bipolar NE555. Other 555 timers can have different specifications depending on the grade (industrial, military, medical, etc.).

Part numberNE555
IC ProcessBipolar
Supply voltage (VCC)4.5 to 16 V
Supply current (VCC = +5 V)3 to 6 mA
Supply current (VCC = +15 V)10 to 15 mA
Output current (maximum)200 mA
Maximum Power dissipation600  mW
Power consumption (minimum operating)30 mW @ 5 V,
225 mW @ 15 V
Operating temperature 0 to 70 °C

Derivatives

Numerous companies have manufactured one or more variants of the 555, 556, 558 timers over the past decades, under many different part numbers. The following is a partial list:

ManufacturerPart
number
Production
status
IC
process
Timers
total
Supply
min. (volt)
Supply
max. (volt)
Iq (μA)
at 5 V
supply
Frequency
max. (MHz)
RemarksDatasheet
Custom Silicon Solutions (CSS)CSS555Active CMOS 11.25.54.31.0Internal EEPROM, requires programmer [30] [31] [32]
Diodes Inc ZSCT1555DiscontinuedBipolar10.961500.33Designed by Hans Camenzind [33]
Japan Radio Company (JRC)NJM555DiscontinuedBipolar14.51630000.1*Also available in SIP-8 package. [28]
Microchip MIC1555/7ActiveCMOS1*2.7182405.0*Reduced pins & features (only astable & monostable & no reset for MIC1555, astable only for MIC1557), only available in SOT23-5, TSOT23-5, UTDFN-10 packages. [29]
ON MC1455ActiveBipolar14.51630000.1* [34]
Renesas ICM7555ActiveCMOS1218401.0 [17]
RenesasICM7556ActiveCMOS2218801.0 [17]
Signetics NE555Active (TI)Bipolar14.51630000.1*First 555 timer, DIP-8 or TO5-8 packages. [4] [16] [35] [2]
SigneticsNE556Active (TI)Bipolar24.51660000.1*First 556 timer, DIP-14 package. [16] [2]
SigneticsNE558DiscontinuedBipolar4*4.5164800*0.1*First 558 timer, DIP-16 package. [2]
STMicroelectronics (ST)TS555ActiveCMOS12161102.7 [36]
Texas Instruments (TI)LM555ActiveBipolar14.51630000.1 [25]
Texas InstrumentsLM556DiscontinuedBipolar24.51660000.1 [37]
Texas InstrumentsLMC555ActiveCMOS11.5151003.0Also available in DSBGA-8 package. [18]
Texas InstrumentsNE555ActiveBipolar14.51630000.1* [1]
Texas InstrumentsNE556ActiveBipolar24.51660000.1* [21]
Texas InstrumentsTLC551ActiveCMOS11151701.8 [20]
Texas InstrumentsTLC552ActiveCMOS21153401.8 [38]
Texas InstrumentsTLC555ActiveCMOS12151702.1 [19]
Texas InstrumentsTLC556ActiveCMOS22153402.1 [39]
X-RELXTR655Active SOI 12.85.51704.0Extreme (−60 °C to +230 °C), ceramic DIP-8 package or bare die. [40]
Table notes

556 dual timer

Die of a NE556 dual timer manufactured by STMicroelectronics STM-NE556-HD.jpg
Die of a NE556 dual timer manufactured by STMicroelectronics
Pinout of 556 dual timer NE556 pennen.svg
Pinout of 556 dual timer

The dual version is called 556. It features two complete 555 timers in a 14-pin package; only the two power-supply pins are shared between the two timers. [21] [16] In 2020, the bipolar version was available as the NE556, [21] and the CMOS versions were available as the Intersil ICM7556 and Texas Instruments TLC556 and TLC552. See derivatives table in this article. [17] [39] [38]

558 quad timer

Die of a NE558 quad timer manufactured by Signetics Signetics Corporation NE558D 0136O07 9331KK KOREA.jpg
Die of a NE558 quad timer manufactured by Signetics
Pinout of 558 quad timer NE558 pennen.svg
Pinout of 558 quad timer
558 internal block diagram. It is different from 555 and 556 timers. NE558 intern.svg
558 internal block diagram. It is different from 555 and 556 timers.

The quad version is called 558 and has four reduced-functionality timers in a 16-pin package designed primarily for monostable multivibrator applications. [49] [2] By 2014, many versions of 16-pin NE558 have become obsolete. [50]

Partial list of differences between 558 and 555 chips: [2] [50]

See also

Notes

  1. ln(2) is a constant, approximately 0.693147 (rounded to 6 significant digits), or commonly rounded to fewer digits in 555 timer books and datasheets to 0.693, 0.69, or 0.7
  2. ln(3) is a constant, approximately 1.098612 (rounded to 6 significant digits), or commonly rounded to fewer digits in 555 timer books and datasheets to 1.099 or 1.1

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A Widlar current source is a modification of the basic two-transistor current mirror that incorporates an emitter degeneration resistor for only the output transistor, enabling the current source to generate low currents using only moderate resistor values.

This article illustrates some typical operational amplifier applications. A non-ideal operational amplifier's equivalent circuit has a finite input impedance, a non-zero output impedance, and a finite gain. A real op-amp has a number of non-ideal features as shown in the diagram, but here a simplified schematic notation is used, many details such as device selection and power supply connections are not shown. Operational amplifiers are optimised for use with negative feedback, and this article discusses only negative-feedback applications. When positive feedback is required, a comparator is usually more appropriate. See Comparator applications for further information.

An avalanche transistor is a bipolar junction transistor designed for operation in the region of its collector-current/collector-to-emitter voltage characteristics beyond the collector-to-emitter breakdown voltage, called avalanche breakdown region. This region is characterized by avalanche breakdown, which is a phenomenon similar to Townsend discharge for gases, and negative differential resistance. Operation in the avalanche breakdown region is called avalanche-mode operation: it gives avalanche transistors the ability to switch very high currents with less than a nanosecond rise and fall times. Transistors not specifically designed for the purpose can have reasonably consistent avalanche properties; for example 82% of samples of the 15V high-speed switch 2N2369, manufactured over a 12-year period, were capable of generating avalanche breakdown pulses with rise time of 350 ps or less, using a 90V power supply as Jim Williams writes.

<span class="mw-page-title-main">Electronic symbol</span> Pictogram used to represent various electrical and electronic devices or functions

An electronic symbol is a pictogram used to represent various electrical and electronic devices or functions, such as wires, batteries, resistors, and transistors, in a schematic diagram of an electrical or electronic circuit. These symbols are largely standardized internationally today, but may vary from country to country, or engineering discipline, based on traditional conventions.

<span class="mw-page-title-main">Pearson–Anson effect</span>

The Pearson–Anson effect, discovered in 1922 by Stephen Oswald Pearson and Horatio Saint George Anson, is the phenomenon of an oscillating electric voltage produced by a neon bulb connected across a capacitor, when a direct current is applied through a resistor. This circuit, now called the Pearson-Anson oscillator, neon lamp oscillator, or sawtooth oscillator, is one of the simplest types of relaxation oscillator. It generates a sawtooth output waveform. It has been used in low frequency applications such as blinking warning lights, stroboscopes, tone generators in electronic organs and other electronic music circuits, and in time bases and deflection circuits of early cathode-ray tube oscilloscopes. Since the development of microelectronics, these simple negative resistance oscillators have been superseded in many applications by more flexible semiconductor relaxation oscillators such as the 555 timer IC.

<span class="mw-page-title-main">Flyback diode</span> Voltage-spike stopping diode across an inductor

A flyback diode is any diode connected across an inductor used to eliminate flyback, which is the sudden voltage spike seen across an inductive load when its supply current is suddenly reduced or interrupted. It is used in circuits in which inductive loads are controlled by switches, and in switching power supplies and inverters.

<span class="mw-page-title-main">Bipolar transistor biasing</span> Process necessary for BJT amplifiers to work correctly

Bipolar transistors must be properly biased to operate correctly. In circuits made with individual devices, biasing networks consisting of resistors are commonly employed. Much more elaborate biasing arrangements are used in integrated circuits, for example, bandgap voltage references and current mirrors. The voltage divider configuration achieves the correct voltages by the use of resistors in certain patterns. By selecting the proper resistor values, stable current levels can be achieved that vary only little over temperature and with transistor properties such as β.

<span class="mw-page-title-main">Intersil ICL8038</span>

The ICL8038 waveform generator was an Integrated circuit by Intersil designed to generate sine, square and triangular waveforms, based on bipolar monolithic technology involving Schottky barrier diodes. ICL8038 was a voltage-controlled oscillator capable of producing frequencies between a millihertz and 100 kHz., some specimens capable of reaching 300 kHz. The device has been discontinued by Intersil in 2002.

<span class="mw-page-title-main">TL431</span> Linear integrated circuit precision shunt regulator

The TL431 integrated circuit (IC) is a three-terminal adjustable precise shunt voltage regulator. With the use of an external voltage divider, a TL431 can regulate voltages ranging from 2.495 to 36 V, at currents up 100 mA. The typical initial deviation of reference voltage from the nominal 2.495 V level is measured in millivolts, the maximum worst-case deviation is measured in tens of millivolts. The circuit can control power transistors directly; combinations of the TL431 with power MOS transistors are used in high efficiency, very low dropout linear regulators. The TL431 is the de facto industry standard error amplifier circuit for switched-mode power supplies with optoelectronic coupling of the input and output networks.

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Further reading

Books
Books with timer chapters
Datasheets