Flat no-leads package

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28-pin QFN, upside down to show contacts and thermal/ground pad 28 pin MLP integrated circuit.jpg
28-pin QFN, upside down to show contacts and thermal/ground pad

Flat no-leads packages such as quad-flat no-leads (QFN) and dual-flat no-leads (DFN) physically and electrically connect integrated circuits to printed circuit boards. Flat no-leads, also known as micro leadframe (MLF) and SON (small-outline no leads), is a surface-mount technology, one of several package technologies that connect ICs to the surfaces of PCBs without through-holes. Flat no-lead is a near chip scale plastic encapsulated package made with a planar copper lead frame substrate. Perimeter lands on the package bottom provide electrical connections to the PCB. [1] Flat no-lead packages usually, but not always, include an exposed thermally conductive pad to improve heat transfer out of the IC (into the PCB). Heat transfer can be further facilitated by metal vias in the thermal pad. [2] The QFN package is similar to the quad-flat package (QFP), and a ball grid array (BGA).

Contents

Flat no-lead cross-section

QFN side view. QFN sideview.svg
QFN side view.

The figure shows the cross section of a flat no-lead package with a lead frame and wire bonding. There are two types of body designs, punch singulation and saw singulation. [3] Saw singulation cuts a large set of packages in parts. In punch singulation, a single package is moulded into shape. The cross section shows a saw-singulated body with an attached thermal head pad. The lead frame is made of copper alloy and a thermally conductive adhesive is used for attaching the silicon die to the thermal pad. The silicon die is electrically connected to the lead frame by 1–2  thou diameter gold wires.

The pads of a saw-singulated package can either be completely under the package, or they can fold around the edge of the package.

Different types

Two types of QFN packages are common: air-cavity QFNs, with an air cavity designed into the package, and plastic-moulded QFNs with air in the package minimized.

Less-expensive plastic-moulded QFNs are usually limited to applications up to ~2–3 GHz. It is usually composed of just 2 parts, a plastic compound and copper lead frame, and does not come with a lid.

In contrast, the air-cavity QFN is usually made up of three parts; a copper leadframe, plastic-moulded body (open, and not sealed), and either a ceramic or plastic lid. It is usually more expensive due to its construction, and can be used for microwave applications up to 20–25 GHz.

QFN packages can have a single row of contacts or a double row of contacts.

Advantages

This package offers a variety of benefits including reduced lead inductance, a small sized "near chip scale" footprint, thin profile and low weight. It also uses perimeter I/O pads to ease PCB trace routing, and the exposed copper die-pad technology offers good thermal and electrical performance. These features make the QFN an ideal choice for many new applications where size, weight, thermal and electrical performance are important.

Design, manufacturing, and reliability challenges

Improved packaging technologies and component miniaturization can often lead to new or unexpected design, manufacturing, and reliability issues. This has been the case with QFN packages, especially when it comes to adoption by new non-consumer electronic OEMs.

Design and manufacturing

Some key QFN design considerations are pad and stencil design. When it comes to bond pad design two approaches can be taken: solder mask defined (SMD) or non-solder mask defined (NSMD). A NSMD approach typically leads to more reliable joints, since the solder is able to bond to both the top and sides of the copper pad. [4] The copper etching process also generally has tighter control than the solder masking process, resulting in more consistent joints. [5] This does have the potential to affect the thermal and electrical performance of the joints, so it can be helpful to consult the package manufacturer for optimal performance parameters. SMD pads can be used to reduce the chances of solder bridging, however this may affect overall reliability of the joints. Stencil design is another key parameter in QFN design process. Proper aperture design and stencil thickness can help produce more consistent joints (i.e. minimal voiding, outgassing, and floating parts) with proper thickness, leading to improved reliability. [6]

There are also issues on the manufacturing side. For larger QFN components, moisture absorption during solder reflow can be a concern. If there is a large amount of moisture absorption into the package then heating during reflow can lead to excessive component warpage. This often results in the corners of the component lifting off the printed circuit board, causing improper joint formation. To reduce the risk of warpage issues during reflow a moisture sensitivity level of 3 or higher is recommended. [7] Several other issues with QFN manufacturing include: part floating due to excessive solder paste under the center thermal pad, large solder voiding, poor reworkable characteristics, and optimization of the solder reflow profile. [8]

Reliability

Component packaging is often driven by the consumer electronics market with less consideration given to higher reliability industries such as automotive and aviation. It can therefore be challenging to integrate component package families, such as the QFN, into high reliability environments. QFN components are known to be susceptible to solder fatigue issues, especially thermomechanical fatigue due to thermal cycling. The significantly lower standoff in QFN packages can lead to higher thermomechanical strains due to coefficient of thermal expansion (CTE) mismatch as compared to leaded packages. For example, under accelerated thermal cycling conditions between -40 °C to 125 °C, various quad flat package (QFP) components can last over 10,000 thermal cycles whereas QFN components tend to fail at around 1,000-3,000 cycles. [7]

Historically, reliability testing has been mainly driven by JEDEC, [9] [10] [11] [12] however this has primarily focused on die and 1st level interconnects. IPC-9071A [13] attempted to address this by focusing on 2nd level interconnects (i.e. package to PCB substrate). The challenge with this standard is that it has been more adopted by OEMs than component manufacturers, who tend to view it as an application-specific issue. As a result there has been much experimental testing and finite element analysis across various QFN package variants to characterize their reliability and solder fatigue behavior. [14] [15] [16] [17] [18] [19] [20]

Serebreni et al. [21] proposed a semi-analytical model to assess the reliability QFN solder joints under thermal cycling. This model generates effective mechanical properties for the QFN package, and calculates the shear stress and strain using a model proposed by Chen and Nelson. [22] The dissipated strain energy density is then determined from these values and used to predict characteristic cycles to failure using a 2-parameter Weibull curve.

Comparison to other packages

The QFN package is similar to the quad flat package, but the leads do not extend out from the package sides. It is hence difficult to hand-solder a QFN package, inspect solder joint quality, or probe lead(s).

Variants

Different manufacturers use different names for this package: ML (micro-leadframe) versus FN (flat no-lead), in addition there are versions with pads on all four sides (quad) and pads on just two sides (dual), thickness varying between 0.9–1.0 mm for normal packages and 0.4 mm for extremely thin. Abbreviations include:

PackageManufacturer
DFNdual flat no-lead packageAtmel, ROHM Semiconductor
DQFNdual quad flat no-lead packageAtmel
cDFN iC-Haus
TDFNthin dual flat no-lead package
UTDFNultra-thin dual flat no-lead package
XDFNextremely thin dual flat no-lead package
QFNquad flat no-lead package Amkor Technology
QFN-TEPquad flat no-lead package with top-exposed pad
TQFNthin quad flat no-lead package
LLPleadless leadframe package National Semiconductor
LPCCleadless plastic chip carrierASAT Holdings
MLFmicro-leadframeAmkor Technology and Atmel
MLPDmicro-leadframe package dual
MLPMmicro-leadframe package micro
MLPQmicro-leadframe package quad
DRMLFdual-row micro-leadframe package Amkor Technology
DRQFNdual-row quad flat no-lead Microchip Technology
VQFN/WQFNvery thin quad flat no-lead Texas Instruments and others (such as Atmel, ROHM Semiconductor)
HVQFNHeatsink Very-thin Quad Flat package
UDFNultra dual flat no-lead Microchip Technology
UQFNultrathin quad flat no-lead Texas Instruments and Microchip Technology
Micro lead frame package Ic-package-MLP-28L.svg
Micro lead frame package

Micro lead frame package (MLP) is a family of integrated circuit QFN packages, used in surface mounted electronic circuits designs. It is available in 3 versions which are MLPQ (Q stands for quad), MLPM (M stands for micro), and MLPD (D stands for dual). These package generally have an exposed die attach pad to improve thermal performance. This package is similar to chip scale packages (CSP) in construction. MLPD are designed to provide a footprint-compatible replacement for small-outline integrated circuit (SOIC) packages.

Micro lead frame (MLF) is a near CSP plastic encapsulated package with a copper leadframe substrate. This package uses perimeter lands on the bottom of the package to provide electrical contact to the printed circuit board. The die attach paddle is exposed on the bottom of the package surface to provide an efficient heat path when soldered directly to the circuit board. This also enables stable ground by use of down bonds or by electrical connection through a conductive die attach material.

A more recent design variation which allows for higher density connections is the dual row micro lead frame (DRMLF) package. This is an MLF package with two rows of lands for devices requiring up to 164 I/O. Typical applications include hard disk drives, USB controllers, and wireless LAN.

See also

Related Research Articles

<span class="mw-page-title-main">Printed circuit board</span> Board to support and connect electronic components

A printed circuit board (PCB), also called printed wiring board (PWB), is a medium used to connect or "wire" components to one another in a circuit. It takes the form of a laminated sandwich structure of conductive and insulating layers: each of the conductive layers is designed with a pattern of traces, planes and other features etched from one or more sheet layers of copper laminated onto and/or between sheet layers of a non-conductive substrate. Electrical components may be fixed to conductive pads on the outer layers in the shape designed to accept the component's terminals, generally by means of soldering, to both electrically connect and mechanically fasten them to it. Another manufacturing process adds vias, plated-through holes that allow interconnections between layers.

<span class="mw-page-title-main">Ball grid array</span> Surface-mount packaging that uses an array of solder balls

A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter. The traces connecting the package's leads to the wires or balls which connect the die to package are also on average shorter than with a perimeter-only type, leading to better performance at high speeds.

<span class="mw-page-title-main">Surface-mount technology</span> Method for producing electronic circuits

Surface-mount technology (SMT), originally called planar mounting, is a method in which the electrical components are mounted directly onto the surface of a printed circuit board (PCB). An electrical component mounted in this manner is referred to as a surface-mount device (SMD). In industry, this approach has largely replaced the through-hole technology construction method of fitting components, in large part because SMT allows for increased manufacturing automation which reduces cost and improves quality. It also allows for more components to fit on a given area of substrate. Both technologies can be used on the same board, with the through-hole technology often used for components not suitable for surface mounting such as large transformers and heat-sinked power semiconductors.

<span class="mw-page-title-main">Flip chip</span> Technique that flips a microchip upside down to connect it

Flip chip, also known as controlled collapse chip connection or its abbreviation, C4, is a method for interconnecting dies such as semiconductor devices, IC chips, integrated passive devices and microelectromechanical systems (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads. The technique was developed by General Electric's Light Military Electronics Department, Utica, New York. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry, it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is reflowed to complete the interconnect. This is in contrast to wire bonding, in which the chip is mounted upright and fine wires are welded onto the chip pads and lead frame contacts to interconnect the chip pads to external circuitry.

<span class="mw-page-title-main">Quad flat package</span> Surface mount integrated circuit package with "gull wing" pins extending from all sides

A quad flat package (QFP) is a surface-mounted integrated circuit package with "gull wing" leads extending from each of the four sides. Socketing such packages is rare and through-hole mounting is not possible. Versions ranging from 32 to 304 pins with a pitch ranging from 0.4 to 1.0 mm are common. Other special variants include low-profile QFP (LQFP) and thin QFP (TQFP).

<span class="mw-page-title-main">Wave soldering</span> Electronics soldering process

Wave soldering is a bulk soldering process used for the manufacturing of printed circuit boards. The circuit board is passed over a pan of molten solder in which a pump produces an upwelling of solder that looks like a standing wave. As the circuit board makes contact with this wave, the components become soldered to the board. Wave soldering is used for both through-hole printed circuit assemblies, and surface mount. In the latter case, the components are glued onto the surface of a printed circuit board (PCB) by placement equipment, before being run through the molten solder wave. Wave soldering is mainly used in soldering of through hole components.

<span class="mw-page-title-main">Reflow soldering</span> Attachment of electronic components

Reflow soldering is a process in which a solder paste is used to temporarily attach anywhere from one to thousands of tiny electrical components to their contact pads, after which the entire assembly is subjected to controlled heat. The solder paste reflows in a molten state, creating permanent solder joints. Heating may be accomplished by passing the assembly through a reflow oven, under an infrared lamp, or by soldering individual joints with a hot air pencil.

<span class="mw-page-title-main">Rework (electronics)</span> Refinishing operation of an electronic printed circuit board assembly

In electronics, rework is the repair or refinish of a printed circuit board (PCB) assembly, usually involving desoldering and re-soldering of surface-mounted electronic components (SMD). Mass processing techniques are not applicable to single device repair or replacement, and specialized manual techniques by expert personnel using appropriate equipment are required to replace defective components; area array packages such as ball grid array (BGA) devices particularly require expertise and appropriate tools. A hot air gun or hot air station is used to heat devices and melt solder, and specialised tools are used to pick up and position often tiny components. A rework station is a place to do this work—the tools and supplies for this work, typically on a workbench. Other kinds of rework require other tools.

<span class="mw-page-title-main">Selective soldering</span>

Selective soldering is the process of selectively soldering components to printed circuit boards and molded modules that could be damaged by the heat of a reflow oven or wave soldering in a traditional surface-mount technology (SMT) or through-hole technology assembly processes. This usually follows an SMT oven reflow process; parts to be selectively soldered are usually surrounded by parts that have been previously soldered in a surface-mount reflow process, and the selective-solder process must be sufficiently precise to avoid damaging them.

Automated optical inspection (AOI) is an automated visual inspection of printed circuit board (PCB) manufacture where a camera autonomously scans the device under test for both catastrophic failure and quality defects. It is commonly used in the manufacturing process because it is a non-contact test method. It is implemented at many stages through the manufacturing process including bare board inspection, solder paste inspection (SPI), pre-reflow and post-re-flow as well as other stages.

Microvias are used as the interconnects between layers in high density interconnect (HDI) substrates and printed circuit boards (PCBs) to accommodate the high input/output (I/O) density of advanced packages. Driven by portability and wireless communications, the electronics industry strives to produce affordable, light, and reliable products with increased functionality. At the electronic component level, this translates to components with increased I/Os with smaller footprint areas, and on the printed circuit board and package substrate level, to the use of high density interconnects (HDIs).

A semiconductor package is a metal, plastic, glass, or ceramic casing containing one or more discrete semiconductor devices or integrated circuits. Individual components are fabricated on semiconductor wafers before being diced into die, tested, and packaged. The package provides a means for connecting it to the external environment, such as printed circuit board, via leads such as lands, balls, or pins; and protection against threats such as mechanical impact, chemical contamination, and light exposure. Additionally, it helps dissipate heat produced by the device, with or without the aid of a heat spreader. There are thousands of package types in use. Some are defined by international, national, or industry standards, while others are particular to an individual manufacturer.

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<span class="mw-page-title-main">Chip carrier</span> Surface mount technology package for integrated circuits

In electronics, a chip carrier is one of several kinds of surface-mount technology packages for integrated circuits. Connections are made on all four edges of a square package; compared to the internal cavity for mounting the integrated circuit, the package overall size is large.

<span class="mw-page-title-main">Lead frame</span> Metal structure inside a chip package that carries signals from the die to the outside

A lead frame is a metal structure inside a chip package that carries signals from the die to the outside, used in DIP, QFP and other packages where connections to the chip are made on its edges.

Solder fatigue is the mechanical degradation of solder due to deformation under cyclic loading. This can often occur at stress levels below the yield stress of solder as a result of repeated temperature fluctuations, mechanical vibrations, or mechanical loads. Techniques to evaluate solder fatigue behavior include finite element analysis and semi-analytical closed-form equations.

Digital image correlation analyses have applications in material property characterization, displacement measurement, and strain mapping. As such, DIC is becoming an increasingly popular tool when evaluating the thermo-mechanical behavior of electronic components and systems.

References

  1. ↑ Design requirements for outlines of solid state and related products, JEDEC PUBLICATION 95, DESIGN GUIDE 4.23
  2. ↑ Bonnie C. Baker, Smaller Packages = Bigger Thermal Challenges, Microchip Technology Inc.
  3. ↑ "Archived copy" (PDF). Archived from the original (PDF) on 2006-08-28. Retrieved 2008-09-26.{{cite web}}: CS1 maint: archived copy as title (link)
  4. ↑ http://www.dfrsolutions.com/hubfs/Resources/services/Manufacturing-and-Reliability-Challenges-With-QFN.pdf?t=1503583170559 [ bare URL PDF ]
  5. ↑ https://www.microsemi.com/document-portal/doc_view/130006-qfn-an [ bare URL PDF ]
  6. ↑ http://www.dfrsolutions.com/hubfs/Resources/services/Understanding-Criticality-of-Stencil-Aperture-Design-and-Implementation-QFN-Package.pdf [ bare URL PDF ]
  7. 1 2 http://www.dfrsolutions.com/hubfs/Resources/services/The-Reliability-Challenges-of-QFN-Packaging.pdf?t=1502980151115 [ bare URL PDF ]
  8. ↑ http://www.aimsolder.com/sites/default/files/overcoming_the_challenges_of_the_qfn_package_rev_2013.pdf, Seelig, K., and Pigeon, K. "Overcoming the Challenges of the QFN Package," Proceedings of SMTAI, October, 2011.
  9. ↑ JEDEC JESD22-A104D, May 2005, Temperature Cycling
  10. ↑ JEDEC JESD22-A105C, January 2011, Power and Temperature Cycling
  11. ↑ JEDEC JESD22-A106B, June 2004, Thermal Shock
  12. ↑ JEDEC JESD22B113, March 2006, Board Level Cycling Bend Test Method for Interconnect Reliability Characterization of Components for Handheld Electronic Products
  13. ↑ IPC IPC-9701A, February 2006, Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments
  14. ↑ Syed, A. and Kang, W. "Board level assembly and reliability considerations for QFN type packages." SMTA International Conference, 2003
  15. ↑ Yan Tee, T., et al. "Comprehensive board-level solder joint reliability modeling and testing of QFN and PowerQFN packages." Microelectronics Reliability 43 (2003): 1329–1338.
  16. ↑ Vianco, P. and Neilsen, M. K. "Thermal mechanical fatigue of a 56 I/O plastic quad-flat nolead (PQFN) package." SMTA International Conference, 2015.
  17. ↑ Wilde, J., and Zukowski, E. "Comparative Analysis for μBGA and QFN Reliability." 8th. Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2007 IEEE, 2007.
  18. ↑ De Vries, J., et al. "Solder-joint reliability of HVQFN-packages subjected to thermal cycling." Microelectronics Reliability 49 (2009): 331-339.
  19. ↑ 17. Li, L. et al. "Board level reliability and assembly process of advanced QFN packages." SMTA International Conference, 2012.
  20. ↑ Birzer, C., et al. "Reliability Investigations of Leadless QFN Packages until End-of-Life with Application-Specific Board-Level Stress Tests." Electronics Components and Technology Conference, 2006.
  21. ↑ Serebreni, M., Blattau, N., Sharon, G., Hillman, C., Mccluskey, P. "Semi-analytical fatigue life model for reliability assessment of solder joints in qfn packages under thermal cycling". SMTA ICSR, 2017. Toronto, ON.
  22. ↑ Chen, W. T., and C. W. Nelson. "Thermal stress in bonded joints." IBM Journal of Research and Development 23.2 (1979): 179-188.
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