Espresso (processor)

Last updated
Espresso
Nintendo-Wii-U-MCM.jpg
An illustration of the Wii U MCM without heat spreader. The smaller chip, lower right, is the "Espresso" CPU made by IBM. The other chips are the "Latte" GPU (large chip, center) from AMD and an EEPROM chip (tiny chip, upper right) from Renesas.
General information
Launched2012
DiscontinuedJanuary 31, 2017
Marketed by Nintendo
Designed by IBM, Nintendo IRD, NTD
Common manufacturer
Performance
Max. CPU clock rate 1.243 GHz
Cache
L2 cache 2 MB, 2× 512 KB (on-die)
Last level cache3
Architecture and classification
ApplicationEmbedded (Wii U)
Technology node 45 nm
Microarchitecture Not verified by Nintendo
Instruction set PowerPC 1.1
Instructions4
Physical specifications
Cores
  • 3
GPU AMD Radeon-based "Latte"
History
Predecessor Broadway
Successor Erista

Espresso is the codename of the 32-bit central processing unit (CPU) used in Nintendo's Wii U video game console. It was designed by IBM, and was produced using a 45 nm silicon-on-insulator process. The Espresso chip resides together with a GPU from AMD on an MCM manufactured by Renesas. It was revealed at E3 2011 in June 2011 and released in November 2012.

Contents

Design

An illustration of the Wii U MCM with heat spreader. The markings indicate that it is designed by Nintendo, and its components are made by AMD, IBM and Renesas. It also says that it was assembled in Japan, the 26th week of 2012. Nintendo-Wii-U-processor-heatspreader.jpg
An illustration of the Wii U MCM with heat spreader. The markings indicate that it is designed by Nintendo, and its components are made by AMD, IBM and Renesas. It also says that it was assembled in Japan, the 26th week of 2012.
Wii U MCM without heat spreader. Espresso is the black rectangle in the top left. Wii U CPU GPU.jpg
Wii U MCM without heat spreader. Espresso is the black rectangle in the top left.

IBM and Nintendo have revealed that the Espresso processor is a PowerPC-based microprocessor with three cores on a single chip to reduce power consumption and increase speed. The CPU and the graphics processor are placed on a single substrate as a multi-chip module (MCM) to reduce complexity, increase the communication speed between the chips, further reduce power consumption, and reduce cost and space required. The two chips were assembled to the complete MCM by Renesas in Japan. [1] Espresso itself was manufactured by IBM in its 300 mm plant in East Fishkill, New York, using 45 nm SOI-technology [2] and embedded DRAM (eDRAM) for caches.

While unverified by Nintendo, hackers, teardowns, and unofficial informants have since revealed more information about the Espresso, such as its name, [3] size [4] [5] and speed. [6] [7] The microarchitecture seems to be quite similar to its predecessors the Broadway and Gekko, i.e. PowerPC 750 based, but enhanced with larger and faster caches and multiprocessor support.

Rumors that the Wii U CPU was derived from IBM's high-end POWER7 server processor proved false, as it would potentially increase the manufacturing and retail cost of the system, and require a larger form factor. Espresso shares some technology with POWER7, such as eDRAM and general instruction set similarities, but those are superficial similarities. [8] [9] [10] [11] [12]

Specifications

The following specifications have not been officially confirmed by either Nintendo or IBM. They have been obtained by reverse engineering by hacker Hector Martin, alias marcan. [13]

Related Research Articles

<span class="mw-page-title-main">PowerPC</span> RISC instruction set architecture by AIM alliance

PowerPC is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple–IBM–Motorola alliance, known as AIM. PowerPC, as an evolving instruction set, has been named Power ISA since 2006, while the old name lives on as a trademark for some implementations of Power Architecture–based processors.

The PowerPC 7xx is a family of third generation 32-bit PowerPC microprocessors designed and manufactured by IBM and Motorola. This family is called the PowerPC G3 by Apple Computer, which introduced it on November 10, 1997. A number of microprocessors from different vendors have been used under the "PowerPC G3" name. Such designations were applied to Mac computers such as the PowerBook G3, the multicolored iMacs, iBooks and several desktops, including both the Beige and Blue and White Power Macintosh G3s. The low power requirements and small size made the processors ideal for laptops and the name lived out its last days at Apple in the iBook.

PowerPC G4 is a designation formerly used by Apple to describe a fourth generation of 32-bit PowerPC microprocessors. Apple has applied this name to various processor models from Freescale, a former part of Motorola. Motorola and Freescale's proper name of this family of processors is PowerPC 74xx.

<span class="mw-page-title-main">POWER4</span> 2001 family of microprocessors by IBM

The POWER4 is a microprocessor developed by International Business Machines (IBM) that implemented the 64-bit PowerPC and PowerPC AS instruction set architectures. Released in 2001, the POWER4 succeeded the POWER3 and RS64 microprocessors, enabling RS/6000 and eServer iSeries models of AS/400 computer servers to run on the same processor, as a step toward converging the two lines. The POWER4 was a multicore microprocessor, with two cores on a single die, the first non-embedded microprocessor to do so. POWER4 Chip was first commercially available multiprocessor chip. The original POWER4 had a clock speed of 1.1 and 1.3 GHz, while an enhanced version, the POWER4+, reached a clock speed of 1.9 GHz. The PowerPC 970 is a derivative of the POWER4.

<span class="mw-page-title-main">POWER7</span> 2010 family of multi-core microprocessors by IBM

POWER7 is a family of superscalar multi-core microprocessors based on the Power ISA 2.06 instruction set architecture released in 2010 that succeeded the POWER6 and POWER6+. POWER7 was developed by IBM at several sites including IBM's Rochester, MN; Austin, TX; Essex Junction, VT; T. J. Watson Research Center, NY; Bromont, QC and IBM Deutschland Research & Development GmbH, Böblingen, Germany laboratories. IBM announced servers based on POWER7 on 8 February 2010.

The PowerPC 400 family is a line of 32-bit embedded RISC processor cores based on the PowerPC or Power ISA instruction set architectures. The cores are designed to fit inside specialized applications ranging from system-on-a-chip (SoC) microcontrollers, network appliances, application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) to set-top boxes, storage devices and supercomputers.

Embedded DRAM (eDRAM) is dynamic random-access memory (DRAM) integrated on the same die or multi-chip module (MCM) of an application-specific integrated circuit (ASIC) or microprocessor. eDRAM's cost-per-bit is higher when compared to equivalent standalone DRAM chips used as external memory, but the performance advantages of placing eDRAM onto the same chip as the processor outweigh the cost disadvantages in many applications. In performance and size, eDRAM is positioned between level 3 cache and conventional DRAM on the memory bus, and effectively functions as a level 4 cache, though architectural descriptions may not explicitly refer to it in those terms.

<span class="mw-page-title-main">Multi-chip module</span> Electronic assembly containing multiple integrated circuits that behaves as a unit

A multi-chip module (MCM) is generically an electronic assembly where multiple integrated circuits, semiconductor dies and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it can be treated as if it were a larger IC. Other terms for MCM packaging include "heterogeneous integration" or "hybrid integrated circuit". The advantage of using MCM packaging is it allows a manufacturer to use multiple components for modularity and/or to improve yields over a conventional monolithic IC approach.

<span class="mw-page-title-main">Broadway (processor)</span> 32-bit CPU for the Wii

Broadway is the codename of the 32-bit central processing unit (CPU) used in Nintendo's Wii home video game console. It was designed by IBM, and was initially produced using a 90 nm SOI process and later produced with a 65 nm SOI process.

<span class="mw-page-title-main">Xenon (processor)</span> CPU used in the Xbox 360

Microsoft XCPU, codenamed Xenon, is a CPU used in the Xbox 360 game console, to be used with ATI's Xenos graphics chip.

The transistor count is the number of transistors in an electronic device. It is the most common measure of integrated circuit complexity. The rate at which MOS transistor counts have increased generally follows Moore's law, which observes that transistor count doubles approximately every two years. However, being directly proportional to the area of a die, transistor count does not represent how advanced the corresponding manufacturing technology is. A better indication of this is transistor density which is the ratio of a semiconductor's transistor count to its die area.

<span class="mw-page-title-main">Gekko (processor)</span> CPU for the GameCube

Gekko is a superscalar out-of-order 32-bit PowerPC microprocessor custom-made by IBM in 2000 for Nintendo to use as the CPU in their sixth generation game console, the GameCube, and later the Triforce Arcade Board.

<span class="mw-page-title-main">PERCS</span>

PERCS is IBM's answer to DARPA's High Productivity Computing Systems (HPCS) initiative. The program resulted in commercial development and deployment of the Power 775, a supercomputer design with extremely high performance ratios in fabric and memory bandwidth, as well as very high performance density and power efficiency.

The IBM A2 is an open source massively multicore capable and multithreaded 64-bit Power ISA processor core designed by IBM using the Power ISA v.2.06 specification. Versions of processors based on the A2 core range from a 2.3 GHz version with 16 cores consuming 65 W to a less powerful, four core version, consuming 20 W at 1.4 GHz.

<span class="mw-page-title-main">POWER8</span> 2014 family of multi-core microprocessors by IBM

POWER8 is a family of superscalar multi-core microprocessors based on the Power ISA, announced in August 2013 at the Hot Chips conference. The designs are available for licensing under the OpenPOWER Foundation, which is the first time for such availability of IBM's highest-end processors.

The zEC12 microprocessor is a chip made by IBM for their zEnterprise EC12 and zEnterprise BC12 mainframe computers, announced on August 28, 2012. It is manufactured at the East Fishkill, New York fabrication plant. The processor began shipping in the fall of 2012. IBM stated that it was the world's fastest microprocessor and is about 25% faster than its predecessor the z196.

IBM Power microprocessors are designed and sold by IBM for servers and supercomputers. The name "POWER" was originally presented as an acronym for "Performance Optimization With Enhanced RISC". The Power line of microprocessors has been used in IBM's RS/6000, AS/400, pSeries, iSeries, System p, System i, and Power Systems lines of servers and supercomputers. They have also been used in data storage devices and workstations by IBM and by other server manufacturers like Bull and Hitachi.

References

  1. "Wii U : The Console : Changes in Television". Iwata Asks. Nintendo. Archived from the original on 2022-06-09.
  2. "NEW WII U™ ON SOI". Archived from the original on 2016-03-25.
  3. "World Exclusive: Wii U Final Specs". 11 September 2012.
  4. "Nintendo Wii U Teardown". AnandTech .
  5. "Nintendo Wii U Teardown". iFixit . 19 November 2012.
  6. "Wii U has 1.24GHz CPU, 550MHz graphics core". Eurogamer.net. 29 November 2012.
  7. "Wii U CPU, GPU Details Uncovered". 29 November 2012.
  8. "IBM puts Watson's brains in Nintendo Wii U".
  9. "IBM teases on Wii U CPU specs". Eurogamer.net. 8 June 2011.
  10. "Rumored Wii U Specs Raising Eyebrows... for the Wrong Reasons".
  11. "IBM reconfirms the Wii U/Watson connection". 27 August 2012.
  12. "IBM Confirms WII U Utilizes Power-Based CPU, Not Power 7". 25 September 2012.
  13. Joel Hruska (November 29, 2012). "Hackers Discover Wii U's Processor Design and Clock Speed". HotHardware . Retrieved January 21, 2014.
  14. Martín, Héctor [@marcan42] (2012-12-09). "@DFaker no, it's just a 750. PPC750 can issue 3/cycle and retire 2/cycle. @dampflokfreund yes, three Broadways and more cache" (Tweet). Archived from the original on 2013-10-05 via Twitter.
  15. Martín, Héctor [@marcan42] (2013-11-23). "Hah! My Twitter arguing must be so sad that I just got this screenshot in my inbox (anon sender): https://marcansoft.com/transf/espresso_intro.png … @EyeOfCore" (Tweet). Archived from the original on 2013-12-03 via Twitter. (links to PNG of a page from the IBM Espresso RISC Processor Developer's User Manual)
  16. Martín, Héctor [@marcan42] (2013-01-30). "@theevilmuppet L1 is the same, L2 is different (this is the claimed eDRAM). 512K/2M/512K L2 cache per core (core 1 has more cache)" (Tweet). Archived from the original on 2013-10-08 via Twitter.
  17. 1 2 3 "IBM PowerPC 750CL Microprocessor Revision Level DD2.x Datasheet" (PDF).

Further reading