Tukwila (processor)

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The Itanium 9300 series, code-named Tukwila, is the generation of Intel's Itanium processor family following Itanium 2 and Montecito. It was released on 8 February 2010. It utilizes both multiple processor cores (multi-core) and SMT techniques. The engineers said to be working on this project were from the DEC Alpha project, specifically those who worked on the Alpha 21464 (EV8), which was focused on SMT.

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Named for the city of Tukwila, Washington, Tukwila was previously code-named Tanglewood. The original name is also used by the Tanglewood music festival, and Intel renamed the project in late 2003. [1]

The processor has two to four cores per die and up to 24 MB L3 of on-die cache. They are the first batch of processors to contain more than 2 billion transistors on a single die. [2] [3] This total is made up as follows: [4]

Die size is 21.5×32.5 mm or 698.75 mm².

Xeon compatibility

It was originally stated that Tukwila and its associated chipset would bring socket compatibility between Intel's Xeon and Itanium processors, by introducing a new interconnect called Intel QuickPath Interconnect (QuickPath, previously known as Common System Interface or CSI). This ultimate endeavor would help reduce product development costs for both Intel and its partners, by allowing for greater reuse of components and manufacturing processes. [5] Tukwila is reported to have four "full" QuickPath links and two "half" links. [6]

Whitefield, the first Xeon processor to feature QuickPath, suffered significant project delays and was cancelled. [7] The first Xeon MP processor to feature QuickPath is Beckton. [8]

The released Itanium 9300-series processors are using a separate socket, LGA 1248, which is incompatible with Xeon processors and motherboards.

Comparison table

ModelCoresThreadsCore Clock
(GHz)
Core Clock with
Intel Turbo Boost (GHz)
L3 Cache (MiB) QPI speed
(GT/s)
TDP
(watts)
February 2010 PriceComments
9310241.6N/A104.8130$946Low power consumption
9320481.331.46164.8155$1,614Value
9330481.461.6204.8155$2,059Performance per watt
9340481.61.73204.8185$2,059Price performance
9350481.731.86244.8185$3,838Performance

Successor

The successor is code-named Poulson . It was initially slated for a Q4 2009 release and said to have over four cores, most likely eight. [9] [10]

In 2009 an Intel representative stated that Intel would maintain a two-year development cycle for Itanium, implying Poulson would be released in Q1 2012. [11]

Related Research Articles

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IA-64 Instruction set architecture of the Itanium family of 64-bit Intel microprocessors

IA-64 is the instruction set architecture (ISA) of the Itanium family of 64-bit Intel microprocessors. The basic ISA specification originated at Hewlett-Packard (HP), and was evolved and then implemented in a new processor microarchitecture by Intel with HP's continued partnership and expertise on the underlying EPIC design concepts. In order to establish what was their first new ISA in 20 years and bring an entirely new product line to market, Intel made a massive investment in product definition, design, software development tools, OS, software industry partnerships, and marketing. To support this effort Intel created the largest design team in their history and a new marketing and industry enabling team completely separate from x86. The first Itanium processor, codenamed Merced, was released in 2001.

Hyper-threading Proprietary simultaneous multithreading implementation by Intel

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Pentium Pro Sixth-generation x86 microprocessor by Intel

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Xeon Line of Intel server processors

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The Intel QuickPath Interconnect (QPI) is a point-to-point processor interconnect developed by Intel which replaced the front-side bus (FSB) in Xeon, Itanium, and certain desktop platforms starting in 2008. It increased the scalability and available bandwidth. Prior to the name's announcement, Intel referred to it as Common System Interface (CSI). Earlier incarnations were known as Yet Another Protocol (YAP) and YAP+.

Nehalem (microarchitecture) CPU microarchitecture by Intel

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LGA 1248

LGA 1248 is an Intel CPU Socket for Itanium processors from the 9300-series to the 9700-series. It replaces PAC611 used by Itanium 9100-series processors and adds Intel QuickPath Interconnect functionalities.

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Broadwell (microarchitecture) Fifth model generation of Intel Processor

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References

  1. Michael Kanellos (December 18, 2003). "Intel changes code name of future Itanium".
  2. BBC News (February 4, 2008). "Chips pass two billion milestone".
  3. Sharon Gaudin (2008-02-04). "Intel squeezes 2 billion transistors onto new Itanium chip". Computerworld . Retrieved 2008-02-05.
  4. Intel shows off Tukwila, first 2 billion transistor CPU
  5. "Intel Changes CPU Road Map". PC World . October 25, 2005.
  6. "Intel's Tukwila Confirmed to be Quad Core". 5 May 2006. Archived from the original on 13 January 2009.
  7. "Intel's CSI to outperform AMD's Hypertransport". The Register . 12 December 2005.
  8. Ng, Jansen (10 February 2009). "Intel Aims for Efficiency With New Server Roadmap". DailyTech . Archived from the original on 13 February 2009. Retrieved 2009-02-10.
  9. Intel Server and Workstation Roadmap Image
  10. Ashlee Vance (11 July 2008). "IBM's eight-core Power7 chip to clock in at 4.0GHz". The Register.
  11. "Intel ahead of schedule with new Xeon server chips". Computerworld . 2009-09-22.