Tarari is a company that spun out of Intel in 2002. It has created a range of re-programmable silicon based on Xilinx Virtex-4 FPGA (Field Programmable Gate Array) and ASICs that offload and accelerate really complex algorithms such as XML Parsing, scanning for Computer viruses, email spam and intruders in Intrusion-prevention systems and Unified threat management appliances. As well as inspecting content its Content Processors can also transform content and they are used for XML transformation XSLT, compression, encryption as well as HD Video encoding for WMV and VC-1 formats.
In June 2006, Tarari announced that its next generation chips that will support the AMDTorrenza initiative - and it will incorporate HyperTransport interfaces. HyperTransport based-systems offer a dramatically reduced latency and increased throughput. This is because a HyperTransport connected system allows a co-processor to have direct access to the system's HyperTransport bus, and thus as much access to system resources as other conventional CPUs.
PCI-Express and HyperTransport buses both allow systems to communicate at 20-25Gbit/s versus 4-8Gbit/s for Peripheral Component Interconnect PCI/PCI-X based systems. Just as the latest desktop machines are using PCI-Express for their high-performance graphic cards now servers will be able to use these high speed interconnects to add other hardware-based co-processors.
PCI-Express and HyperTransport buses both operate serially using multiple lanes - PCI-Express supports 1, 2, 4 or 8 lane connectivity at 2.5Gbit/s per lane. Whereas PCI/PCI-X works using parallel transfers and is most efficient in the 2k - 4k byte per transfer range, PCI-Express and HyperTransport are very efficient at transfers as small as just 64 bytes. Therefore, applications such as in intrusion-prevention system (IPS) and VOIP security applications which have to examine a large volume of small packets will benefit from such high-speed and highly efficient transfer capabilities.
On 5 September 2007, LSI Corporation announced a definitive agreement to acquire Tarari.
HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low-latency point-to-point link that was introduced on April 2, 2001. The HyperTransport Consortium is in charge of promoting and developing HyperTransport technology.
InfiniBand (IB) is a computer networking communications standard used in high-performance computing that features very high throughput and very low latency. It is used for data interconnect both among and within computers. InfiniBand is also used as either a direct or switched interconnect between servers and storage systems, as well as an interconnect between storage systems. It is designed to be scalable and uses a switched fabric network topology. Between 2014 and June 2016, it was the most commonly used interconnect in the TOP500 list of supercomputers.
PCI Express, officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common motherboard interface for personal computers' graphics cards, sound cards, hard disk drive host adapters, SSDs, Wi-Fi and Ethernet hardware connections. PCIe has numerous improvements over the older standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance scaling for bus devices, a more detailed error detection and reporting mechanism, and native hot-swap functionality. More recent revisions of the PCIe standard provide hardware support for I/O virtualization.
QuickRing was a gigabit-rate interconnect that combined the functions of a computer bus and a network. It was designed at Apple Computer as a multimedia system to run "on top" of existing local bus systems inside a computer, but was later taken over by National Semiconductor and repositioned as an interconnect for parallel computing. It appears to have seen little use in either role, and is no longer being actively worked on. However it appears to have been an inspiration for other more recent technologies, such as HyperTransport.
The front-side bus (FSB) is a computer communication interface (bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. Both typically carry data between the central processing unit (CPU) and a memory controller hub, known as the northbridge.
TCP offload engine (TOE) is a technology used in some network interface cards (NIC) to offload processing of the entire TCP/IP stack to the network controller. It is primarily used with high-speed network interfaces, such as gigabit Ethernet and 10 Gigabit Ethernet, where processing overhead of the network stack becomes significant. TOEs are often used as a way to reduce the overhead associated with Internet Protocol (IP) storage protocols such as iSCSI and Network File System (NFS).
PCI-X, short for Peripheral Component Interconnect eXtended, is a computer bus and expansion card standard that enhances the 32-bit PCI local bus for higher bandwidth demanded mostly by servers and workstations. It uses a modified protocol to support higher clock speeds, but is otherwise similar in electrical implementation. PCI-X 2.0 added speeds up to 533 MHz, with a reduction in electrical signal levels.
The nForce4 is a motherboard chipset released by Nvidia in October 2004. The chipset supports AMD 64-bit processors and Intel Pentium 4 LGA 775 processors.
The RapidIO architecture is a high-performance packet-switched electrical connection technology. It supports messaging, read/write and cache coherency semantics. Based on industry-standard electrical specifications such as those for Ethernet, RapidIO can be used as a chip-to-chip, board-to-board, and chassis-to-chassis interconnect.
The Intel QuickPath Interconnect (QPI) is a point-to-point processor interconnect developed by Intel which replaced the front-side bus (FSB) in Xeon, Itanium, and certain desktop platforms starting in 2008. It increased the scalability and available bandwidth. Prior to the name's announcement, Intel referred to it as Common System Interface (CSI). Earlier incarnations were known as Yet Another Protocol (YAP) and YAP+.
The System Packet Interface (SPI) family of Interoperability Agreements from the Optical Internetworking Forum specify chip-to-chip, channelized, packet interfaces commonly used in synchronous optical networking and Ethernet applications. A typical application of such a packet level interface is between a framer or a MAC and a network processor. Another application of this interface might be between a packet processor ASIC and a traffic manager device.
The PowerPC 400 family is a line of 32-bit embedded RISC processor cores based on the PowerPC or Power ISA instruction set architectures. The cores are designed to fit inside specialized applications ranging from system-on-a-chip (SoC) microcontrollers, network appliances, application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) to set-top boxes, storage devices and supercomputers.
In computer technology, transfers per second and its more common secondary terms gigatransfers per second (abbreviated as GT/s) and megatransfers per second (MT/s) are informal language that refer to the number of operations transferring data that occur in each second in some given data-transfer channel. It is also known as sample rate, i.e. the number of data samples captured per second, each sample normally occurring at the clock edge. The terms are neutral with respect to the method of physically accomplishing each such data-transfer operation; nevertheless, they are most commonly used in the context of transmission of digital data. 1 MT/s is 106 or one million transfers per second; similarly, 1 GT/s means 109, or equivalently in the US/short scale, one billion transfers per second.
The AMD 700 chipset series is a set of chipsets designed by ATI for AMD Phenom processors to be sold under the AMD brand. Several members were launched in the end of 2007 and the first half of 2008, others launched throughout the rest of 2008.
Universal Serial Bus 3.0, marketed as SuperSpeed USB, is the third major version of the Universal Serial Bus (USB) standard for interfacing computers and electronic devices. It was released in November 2008. The USB 3.0 specification defined a new architecture and protocol, named SuperSpeed, which included a new lane for a new signal coding scheme providing full-duplex data transfers that physically required five additional wires and pins, while preserving the USB 2.0 architecture and protocols and therefore keeping the original four pins and wires for the USB 2.0 backward-compatibility, resulting in nine wires in total and nine or ten pins at connector interfaces. The new transfer rate, marketed as SuperSpeed USB (SS), can transfer signals at up to 5 Gbit/s with nominal data rate of 500 MB/s after encoding overhead, which is about 10 times faster than High-Speed. USB 3.0 Type-A and B connectors are usually blue, to distinguish them from USB 2.0 connectors, as recommended by the specification. and by the initials SS.
M.2, pronounced m dot two and formerly known as the Next Generation Form Factor (NGFF), is a specification for internally mounted computer expansion cards and associated connectors. M.2 replaces the Mini-SATA (mSATA) standard, which uses the PCI Express Mini Card physical card layout and connectors. Employing a more flexible physical specification, M.2 allows different module widths and lengths, which, paired with the availability of more advanced interfacing features, makes M.2 more suitable than mSATA in general for solid-state storage applications, particularly in smaller devices such as ultrabooks and tablets.
SATA Express is a computer bus interface that supports both Serial ATA (SATA) and PCI Express (PCIe) storage devices, initially standardized in the SATA 3.2 specification. The SATA Express connector used on the host side is backward compatible with the standard SATA data connector, while it also provides two PCI Express lanes as a pure PCI Express connection to the storage device.
NVLink is a wire-based serial multi-lane near-range communications link developed by Nvidia. Unlike PCI Express, a device can consist of multiple NVLinks, and devices use mesh networking to communicate instead of a central hub. The protocol was first announced in March 2014 and uses a proprietary high-speed signaling interconnect (NVHS).
Coherent Accelerator Processor Interface (CAPI), is a high-speed processor expansion bus standard for use in large data center computers, initially designed to be layered on top of PCI Express, for directly connecting central processing units (CPUs) to external accelerators like graphics processing units (GPUs), ASICs, FPGAs or fast storage. It offers low latency, high speed, direct memory access connectivity between devices of different instruction set architectures.
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