Microsequencer

Last updated

In computer architecture and engineering, a sequencer or microsequencer generates the addresses used to step through the microprogram of a control store. It is used as a part of the control unit of a CPU or as a stand-alone generator for address ranges.

Contents

Usually the addresses are generated by some combination of a counter, a field from a microinstruction, and some subset of the instruction register. A counter is used for the typical case, that the next microinstruction is the one to execute. A field from the microinstruction is used for jumps, or other logic.

Since CPUs implement an instruction set, it's very useful to be able to decode the instruction's bits directly into the sequencer, to select a set of microinstructions to perform a CPU's instructions.

Most modern CISC processors use a combination of pipelined logic to process lower complexity opcodes which can be completed in one clock cycle, and microcode to implement ones that take multiple clock cycles to complete.

One of the first integrated microcoded processors was the IBM PALM Processor, which emulated all of the processor's instruction in microcode and was used on the IBM 5100, one of the first personal computers.

Recent examples of similar open-sourced microsequencer-based processors are the MicroCore Labs MCL86, MCL51, and MCL65 cores which emulate the Intel 8086/8088, 8051 and MOS 6502 instruction sets entirely in microcode.

Simple example

The Digital Scientific Corp. Meta 4 Series 16 computer system was a user-microprogrammable system first available in 1970. Branches in the microcode sequence occur in one of three ways. [1]

One more sequencing option allowed on a branch instruction is the execute (XQ) option. When specified, the single instruction at the branch address is executed, but then execution continues after the original branch instruction. The IX option can be used with the XQ option.

Complex example

The IBM System/360 was a series of compatible computers introduced in 1964, many of which were microprogrammed. [2] The System/360 Model 40 is a good example of a microprogrammed machine with complex microsequencing. [3]

The microstore consists of 4,096 56-bit microinstructions that operate in a horizontal microprogramming style. The store is addressed by the 12-bit read-only address register (ROAR). Unlike most registers in the S/360 architecture, bits in the ROAR are numbered from bit 0 on the right to bit 11 on the left.

  +------------+   |    ROAR    |   +------------+   11          0 

The model 40 performs no sequential execution of microinstructions and therefore the microsequencer doesn't really branch in the conventional sense. Instead, each microinstruction specifies the address of the next one to be executed. Four fields in the microinstruction contribute to the new address.

There are essentially three combinations or formats of these fields.

Functional branch format

When the CB field contains 15, a functional branch occurs. The bits of the new microstore address in the ROAR are determined as follows.

The CC field can specify various tests of the state of the machine. It can also specify a constant 0 or 1 for an unconditional bit.

This format alters the flow of control to 1 of 16 instruction pairs within the low 32 words of a 64-word block of microstore (because bit 5 is always 0). The CC field then determines which instruction of the pair receives control.

CD = 0, 1, 3 format

When the CD field is 0, 1, or 3, flow of control is directed to an instruction within the current 64-word block. The bits of the new microstore address are determined as follows.

The CA field selects 1 of 16 4-word groups within the current 64-word block. The CB and CC fields then determine which instruction of the 4 receives control.

CD = 2 format

When the CD field is 2, flow of control is directed in a nonobvious manner. The bits of the new microstore address are determined as follows:

The next instruction is in the same 1K-word region as the current instruction, because bits 1110 remain the same. The CA field determines the 64-word block within the region. The instruction is in the same 4-word group within the new block as the current instruction is within the current block, because bits 52 remain the same. The CB and CC fields then determine which instruction of the 4 receives control.

Simplification

This description has been simplified. It ignores the following features.

Related Research Articles

The control unit (CU) is a component of a computer's central processing unit (CPU) that directs the operation of the processor. A CU typically uses a binary decoder to convert coded instructions into timing and control signals that direct the operation of the other units.

A control store is the part of a CPU's control unit that stores the CPU's microprogram. It is usually accessed by a microsequencer. A control store implementation whose contents are unalterable is known as a Read Only Memory (ROM) or Read Only Storage (ROS); one whose contents are alterable is known as a Writable Control Store (WCS).

In processor design, microcode serves as an intermediary layer situated between the central processing unit (CPU) hardware and the programmer-visible instruction set architecture of a computer, also known as its machine code. It consists of a set of hardware-level instructions that implement the higher-level machine code instructions or control internal finite-state machine sequencing in many digital processing components. While microcode is utilized in Intel and AMD general-purpose CPUs in contemporary desktops and laptops, it functions only as a fallback path for scenarios that the faster hardwired control unit is unable to manage.

<span class="mw-page-title-main">Machine code</span> Lowest level instructions executed by a computer

In computer programming, machine code is computer code consisting of machine language instructions, which are used to control a computer's central processing unit (CPU). For conventional binary computers machine code is "the binary representation of a computer program which is actually read and interpreted by the computer. A program in machine code consists of a sequence of machine instructions ."

<span class="mw-page-title-main">PDP-8</span> Minicomputer product line

The PDP-8 is a family of 12-bit minicomputers that was produced by Digital Equipment Corporation (DEC). It was the first commercially successful minicomputer, with over 50,000 units being sold over the model's lifetime. Its basic design follows the pioneering LINC but has a smaller instruction set, which is an expanded version of the PDP-5 instruction set. Similar machines from DEC are the PDP-12 which is a modernized version of the PDP-8 and LINC concepts, and the PDP-14 industrial controller system.

In computer science, an instruction set architecture (ISA) is an abstract model that generally defines how software controls the CPU in a computer or a family of computers. A device or program that executes instructions described by that ISA, such as a central processing unit (CPU), is called an implementation of that ISA.

<span class="mw-page-title-main">IBM System/370</span> Family of mainframe computers 1970–1990

The IBM System/370 (S/370) is a range of IBM mainframe computers announced as the successors to the System/360 family on June 30, 1970. The series mostly maintains backward compatibility with the S/360, allowing an easy migration path for customers; this, plus improved performance, were the dominant themes of the product announcement.

The Motorola 68000 series is a family of 32-bit complex instruction set computer (CISC) microprocessors. During the 1980s and early 1990s, they were popular in personal computers and workstations and were the primary competitors of Intel's x86 microprocessors. They were best known as the processors used in the early Apple Macintosh, the Sharp X68000, the Commodore Amiga, the Sinclair QL, the Atari ST and Falcon, the Atari Jaguar, the Sega Genesis and Sega CD, the Philips CD-i, the Capcom System I (Arcade), the AT&T UNIX PC, the Tandy Model 16/16B/6000, the Sun Microsystems Sun-1, Sun-2 and Sun-3, the NeXT Computer, NeXTcube, NeXTstation, and NeXTcube Turbo, early Silicon Graphics IRIS workstations, the Aesthedes, computers from MASSCOMP, the Texas Instruments TI-89/TI-92 calculators, the Palm Pilot, the Control Data Corporation CDCNET Device Interface, the VTech Precomputer Unlimited and the Space Shuttle. Although no modern desktop computers are based on processors in the 680x0 series, derivative processors are still widely used in embedded systems.

<span class="mw-page-title-main">IBM 700/7000 series</span> Mainframe computer systems made by IBM through the 1950s and early 1960s

The IBM 700/7000 series is a series of large-scale (mainframe) computer systems that were made by IBM through the 1950s and early 1960s. The series includes several different, incompatible processor architectures. The 700s use vacuum-tube logic and were made obsolete by the introduction of the transistorized 7000s. The 7000s, in turn, were eventually replaced with System/360, which was announced in 1964. However the 360/65, the first 360 powerful enough to replace 7000s, did not become available until November 1965. Early problems with OS/360 and the high cost of converting software kept many 7000s in service for years afterward.

<span class="mw-page-title-main">IBM 1130</span> 16-bit IBM minicomputer introduced in 1965

The IBM 1130 Computing System, introduced in 1965, was IBM's least expensive computer at that time. A binary 16-bit machine, it was marketed to price-sensitive, computing-intensive technical markets, like education and engineering, succeeding the decimal IBM 1620 in that market segment. Typical installations included a 1 megabyte disk drive that stored the operating system, compilers and object programs, with program source generated and maintained on punched cards. Fortran was the most common programming language used, but several others, including APL, were available.

Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions in that architecture identify the operand(s) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

z/Architecture, initially and briefly called ESA Modal Extensions (ESAME), is IBM's 64-bit complex instruction set computer (CISC) instruction set architecture, implemented by its mainframe computers. IBM introduced its first z/Architecture-based system, the z900, in late 2000. Later z/Architecture systems include the IBM z800, z990, z890, System z9, System z10, zEnterprise 196, zEnterprise 114, zEC12, zBC12, z13, z14, z15 and z16.

In computing, channel I/O is a high-performance input/output (I/O) architecture that is implemented in various forms on a number of computer architectures, especially on mainframe computers. In the past, channels were generally implemented with custom devices, variously named channel, I/O processor, I/O controller, I/O synchronizer, or DMA controller.

<span class="mw-page-title-main">CVAX</span> Microprocessor chipset

The CVAX is a microprocessor chipset developed and fabricated by Digital Equipment Corporation (DEC) that implemented the VAX instruction set architecture (ISA). The chipset consisted of the CVAX 78034 CPU, CFPA floating-point accelerator, CVAX clock chip, and the associated support chips, the CVAX System Support Chip (CSSC), CVAX Memory Controller (CMCTL), and CVAX Q-Bus Interface Chip (CQBIC).

A control register is a processor register that changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.

<span class="mw-page-title-main">TI-990</span> Series of 16-bit computers by Texas Instruments.

The TI-990 was a series of 16-bit minicomputers sold by Texas Instruments (TI) in the 1970s and 1980s. The TI-990 was a replacement for TI's earlier minicomputer systems, the TI-960 and the TI-980. It had several unique features, and was easier to program than its predecessors.

<span class="mw-page-title-main">History of general-purpose CPUs</span>

The history of general-purpose CPUs is a continuation of the earlier history of computing hardware.

Joel McCormack is an American computer scientist who designed the NCR Corporation version of the p-code machine, which is a kind of stack machine popular in the 1970s as the preferred way to implement new computing architectures and languages such as Pascal and BCPL. The NCR design shares no common architecture with the Pascal MicroEngine designed by Western Digital but both were meant to execute the UCSD p-System.[1,2]

The IBM System/360 architecture is the model independent architecture for the entire S/360 line of mainframe computers, including but not limited to the instruction set architecture. The elements of the architecture are documented in the IBM System/360 Principles of Operation and the IBM System/360 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information manuals.

<span class="mw-page-title-main">IBM System/360 Model 20</span> Low-end IBM computer model from 1960s

The IBM System/360 Model 20 is the smallest member of the IBM System/360 family announced in November 1964. The Model 20 supports only a subset of the System/360 instruction set, with binary numbers limited to 16 bits and no floating point arithmetic. In later years it would have been classified as a 16-bit minicomputer rather than a mainframe, but the term "minicomputer" was not current, and in any case IBM wanted to emphasize the compatibility of the Model 20 rather than its differences from the rest of the System/360 line. It does, however, have the full System/360 decimal instruction set, that allows for addition, subtraction, product, and dividend of up to 31 decimal digits.

References

  1. Digital Scientific Meta 4 Series 16 Computer System Reference Manual (PDF). Digital Scientific Corporation. May 1971. 7032MO.
  2. IBM System/360 Principles of Operation (PDF). International Business Machines Corp. September 1968. A22-6821-7.
  3. System/360 Model 40 Functional Units (PDF). International Business Machines Corp. March 1970. SY22-2843-1.