31-bit computing

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In computer architecture, 31-bit integers, memory addresses, or other data units are those that are 31 bits wide.

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In 1983, IBM introduced 31-bit addressing in the System/370-XA mainframe architecture as an upgrade to the 24-bit physical and virtual, [1] and transitional 24-bit-virtual/26-bit physical, [2] [3] addressing in System/370. [4] [5] This enhancement allowed address spaces to be 128 times larger, permitting programs to address memory above 16  MB (referred to as "above the line"). [6] [1] Support for COBOL, FORTRAN and later on Linux/390 were included.

In the early 1980s, the Motorola 68012 was introduced; it had 32-bit data and address registers, as the Motorola 68010 did, but instead of providing the lower 24 bits of an address on the address pins, it provided all but bit 30 on the address pins. [7]

31-bit computer

The Librascope LGP-30 was an early off-the-shelf computer. The LGP-30 was first manufactured in 1956, [8] at a retail price of $47,000,[ citation needed ]equivalent to $530,000in 2023. [9]

It was a binary, 31-bit word computer with a 4096-word drum memory. There were 32 bit locations per drum word, but only 31 were used, permitting a "restoration of magnetic flux in the head" at the 32nd bit time. The number of vacuum tubes was minimized by using solid-state diode logic, a bit-serial architecture and multiple use of each of its 15 flip-flops.

The LGP-30 was commonly referred to as a desk computer. Its height, width, and depth, excluding the typewriter shelf, was 33 by 44 by 26 inches (84 by 112 by 66 cm). It weighed about 800 pounds (360 kg), and was mounted on sturdy casters which facilitated moving the unit.

IBM mainframes with 31-bit addressing

In the System/360, other than the 360/67, and early System/370 architectures, the general-purpose registers were 32 bits wide, the machine did 32-bit arithmetic operations, and addresses were always stored in 32-bit words, so the architecture was considered 32-bit, but the machines ignored the top 8 bits of the address resulting in 24-bit addressing.

With the System/370-XA architecture and the IBM Enterprise Systems Architecture, in addition to a 24-bit addressing mode for compatibility with older applications, there is a 31-bit addressing mode, in which only the high order bit (bit 0) in the word is ignored for addressing. An exception is that mode-switching instructions also use bit 0. There were at least two reasons that IBM did not implement the 32-bit addressing of the 360/67

  1. The loop control instructions BXH and BXLE did signed comparisons.
  2. Much of the existing software used bit 0 as an end-of-list indicator. [10]

The 64-bit z/Architecture also supports 24-bit and 31-bit addressing modes for compatibility with older applications.

Ruby and Smalltalk

Interpreters for Ruby and Smalltalk languages use the lowest bit to tell whether a value is an unboxed integer or not. This means that on 32-bit machines (or 16-bit machines with 32-bit pointers), 31-bit integers are unboxed. In case of overflow, the result is fit into a boxed object, which means that it has to be allocated and garbage-collected. Thus if you have 32-bit values that don't fit in the 31-bit signed format, they will be very inefficient in those interpreters. Same goes with 63-bit unboxed integers on 64-bit computers. Similar designs may be found in LISP and some of the other languages whose variables can take values of any type. In some cases, there was hardware support for this kind of design: see Tagged architecture and Lisp machine.

Related Research Articles

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<span class="mw-page-title-main">MVS</span> Operating system for IBM mainframes

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<span class="mw-page-title-main">IBM System/360</span> IBM mainframe computer family (1964–1977)

The IBM System/360 (S/360) is a family of mainframe computer systems announced by IBM on April 7, 1964, and delivered between 1965 and 1978. System/360 was the first family of computers designed to cover both commercial and scientific applications and a complete range of applications from small to large. The design distinguished between architecture and implementation, allowing IBM to release a suite of compatible designs at different prices. All but the only partially compatible Model 44 and the most expensive systems use microcode to implement the instruction set, featuring 8-bit byte addressing and fixed point binary, fixed point decimal and hexadecimal floating-point calculations.

<span class="mw-page-title-main">Endianness</span> Order of bytes in a computer word

In computing, endianness is the order in which bytes within a word of digital data are transmitted over a data communication medium or addressed in computer memory, counting only byte significance compared to earliness. Endianness is primarily expressed as big-endian (BE) or little-endian (LE), terms introduced by Danny Cohen into computer science for data ordering in an Internet Experiment Note published in 1980. The adjective endian has its origin in the writings of 18th century Anglo-Irish writer Jonathan Swift. In the 1726 novel Gulliver's Travels, he portrays the conflict between sects of Lilliputians divided into those breaking the shell of a boiled egg from the big end or from the little end. By analogy, a CPU may read a digital word big end first, or little end first.

In computer architecture, 8-bit integers or other data units are those that are 8 bits wide. Also, 8-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers or data buses of that size. Memory addresses for 8-bit CPUs are generally larger than 8-bit, usually 16-bit. 8-bit microcomputers are microcomputers that use 8-bit microprocessors.

<span class="mw-page-title-main">IBM System/370</span> Family of mainframe computers 1970–1990

The IBM System/370 (S/370) is a range of IBM mainframe computers announced as the successors to the System/360 family on June 30, 1970. The series mostly maintains backward compatibility with the S/360, allowing an easy migration path for customers; this, plus improved performance, were the dominant themes of the product announcement.

The 801 was an experimental central processing unit (CPU) design developed by IBM during the 1970s. It is considered to be the first modern RISC design, relying on processor registers for all computations and eliminating the many variant addressing modes found in CISC designs. Originally developed as the processor for a telephone switch, it was later used as the basis for a minicomputer and a number of products for their mainframe line. The initial design was a 24-bit processor; that was soon replaced by 32-bit implementations of the same concepts and the original 24-bit 801 was used only into the early 1980s.

In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculations more efficiently and process more data per clock cycle. Typical 32-bit personal computers also have a 32-bit address bus, permitting up to 4 GB of RAM to be accessed, far more than previous generations of system architecture allowed.

<span class="mw-page-title-main">64-bit computing</span> Computer architecture bit width

In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit central processing units (CPU) and arithmetic logic units (ALU) are those that are based on processor registers, address buses, or data buses of that size. A computer that uses such a processor is a 64-bit computer.

A processor register is a quickly accessible location available to a computer's processor. Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. In computer architecture, registers are typically addressed by mechanisms other than main memory, but may in some cases be assigned a memory address e.g. DEC PDP-10, ICT 1900.

<span class="mw-page-title-main">Memory address</span> Reference to a specific memory location

In computing, a memory address is a reference to a specific memory location used at various levels by software and hardware. Memory addresses are fixed-length sequences of digits conventionally displayed and manipulated as unsigned integers. Such numerical semantic bases itself upon features of CPU, as well upon use of the memory like an array endorsed by various programming languages.

z/Architecture, initially and briefly called ESA Modal Extensions (ESAME), is IBM's 64-bit complex instruction set computer (CISC) instruction set architecture, implemented by its mainframe computers. IBM introduced its first z/Architecture-based system, the z900, in late 2000. Later z/Architecture systems include the IBM z800, z990, z890, System z9, System z10, zEnterprise 196, zEnterprise 114, zEC12, zBC12, z13, z14, z15 and z16.

In computer architecture, 26-bit integers, memory addresses, or other data units are those that are 26 bits wide, and thus can represent unsigned values up to 67,108,863. Two examples of computer processors that featured 26-bit memory addressing are certain second generation IBM System/370 mainframe computer models introduced in 1981, which had 26-bit physical addresses but had only the same 24-bit virtual addresses as earlier models, and the first generations of ARM processors.

The program status word (PSW) is a register that performs the function of a status register and program counter, and sometimes more. The term is also applied to a copy of the PSW in storage. This article only discusses the PSW in the IBM System/360 and its successors, and follows the IBM convention of numbering bits starting with 0 as the leftmost bit.

A control register is a processor register that changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.

An instruction set architecture (ISA) is an abstract model of a computer, also referred to as computer architecture. A realization of an ISA is called an implementation. An ISA permits multiple implementations that may vary in performance, physical size, and monetary cost ; because the ISA serves as the interface between software and hardware. Software that has been written for an ISA can run on different implementations of the same ISA. This has enabled binary compatibility between different generations of computers to be easily achieved, and the development of computer families. Both of these developments have helped to lower the cost of computers and to increase their applicability. For these reasons, the ISA is one of the most important abstractions in computing today.

In computer engineering, a register–memory architecture is an instruction set architecture that allows operations to be performed on memory, as well as registers. If the architecture allows all operands to be in memory or in registers, or in combinations, it is called a "register plus memory" architecture.

IBM System/370-XA is an instruction set architecture introduced by IBM in 1983 with the IBM 308X processors. It extends the IBM System/370 architecture to support 31-bit virtual and physical addresses, and includes a redesigned I/O architecture.

IBM Enterprise Systems Architecture is an instruction set architecture introduced by IBM as ESA/370 in 1988. It is based on the IBM System/370-XA architecture.

References

  1. 1 2 "A brief history of virtual storage and 64-bit addressability". IBM .
  2. ↑ "with transitional support for 26-bit"
  3. ↑ KE Plambeck (2002). "Development and attributes of z/Architecture"" (PDF).
  4. ↑ Robert T. Fertig (May 1983). "XA: The View From The Trenches (pp.122-136)". Datamation.
  5. ↑ Ronald L. Bond (May 1983). "XA: The View From White Plains (pp.139–152)". Datamation.
  6. ↑ "...to run in the 31-bit area above the line,... "Rewriting to run in 31 bit area". Computerworld. October 27, 1986. p. 13.
  7. ↑ "4.1 SIGNAL DESCRIPTION" (PDF). MC68010/MC68012 16-/32-Bit Virtual Memory Microprocessors (PDF). Motorola Semiconductor. May 1985. pp. 4-1–4-2. ADI942R2.{{cite book}}: |work= ignored (help)
  8. ↑ "1950-1959 Librazettes". www.librascopememories.com. Archived from the original on 2014-12-27. Retrieved 2018-03-19. Librazette: July, 1956 – Royal Precision Plans – LGP-30 Promotion; November, 1956 – LGP-30, Flow Computer Spearhead – Commercial Sales and Production – They're In Production and Paul Coates Will Feature LGP-30 on Dec. TVshows[ verification needed ]
  9. ↑ 1634–1699: McCusker, J. J. (1997). How Much Is That in Real Money? A Historical Price Index for Use as a Deflator of Money Values in the Economy of the United States: Addenda et Corrigenda (PDF). American Antiquarian Society. 1700–1799: McCusker, J. J. (1992). How Much Is That in Real Money? A Historical Price Index for Use as a Deflator of Money Values in the Economy of the United States (PDF). American Antiquarian Society. 1800–present: Federal Reserve Bank of Minneapolis. "Consumer Price Index (estimate) 1800–" . Retrieved February 29, 2024.
  10. ↑ "... the high order bit in the last fullword must be set to one to indicate the end of the list." "WAIT — Wait for one or more events". IBM .
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